公开(公告)号：US08065450B2

公开(公告)日：2011-11-22

申请号：US11959640

申请日：2007-12-19

申请人： Hiroshi Kurosaki

发明人： Hiroshi Kurosaki

IPC分类号： G06F12/02

CPC分类号： H04L49/103 ,  H04L49/30 ,  H04L49/3009

摘要： In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

摘要翻译： 在帧传送方法和装置中，即使在共享缓冲器的管理中发生异常操作，也可以在不减少空间的情况下有效地利用共享缓冲器的地址空间，在帧数据被写入共享缓冲器之后 在下一个监视周期中检测到帧数据从共享缓冲器中读取而不是从共享缓冲器中读取的一个监视周期，其中尚未从共享缓冲器读取帧数据的地址空间， 至少在检测到监视周期期间已经执行了帧数据的写入。 在下一个监视周期中，地址空间作为共享缓冲区的空闲地址释放。

公开(公告)号：US20090245258A1

公开(公告)日：2009-10-01

申请号：US12405393

申请日：2009-03-17

申请人： Jun Tanaka ,  Hiroshi Tomonaga ,  Takashi Kuwabara ,  Hiroshi Kurosaki

发明人： Jun Tanaka ,  Hiroshi Tomonaga ,  Takashi Kuwabara ,  Hiroshi Kurosaki

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： H04L45/22 ,  H04L41/0659 ,  H04L45/28 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/351 ,  H04L49/557

摘要： An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

摘要翻译： 一种装置包括输入部分，多个输出部分和切换部分。 输入部分输入分组，构建至少一个转发数据块，该转发数据块包括预定的目的地标识符和从输入的分组提取的分组数据。 切换部分包括转发目的地存储部分，用于与预定的目的地标识符相关联地存储识别多个输出部分之一的转发目的地标识符，并从输入部分接收至少一个转发数据块，并将其转发 基于转发目的地存储部分，响应于多个输出部分的操作状态的改变来更新多个输出部分中的一个输出部分。

公开(公告)号：US20080155202A1

公开(公告)日：2008-06-26

申请号：US11959640

申请日：2007-12-19

申请人： Hiroshi Kurosaki

发明人： Hiroshi Kurosaki

IPC分类号： G06F12/00

CPC分类号： H04L49/103 ,  H04L49/30 ,  H04L49/3009

摘要： In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

摘要翻译： 在帧传送方法和装置中，即使在共享缓冲器的管理中发生异常操作，也可以在不减少空间的情况下有效地利用共享缓冲器的地址空间，在帧数据被写入共享缓冲器之后 在下一个监视周期中检测到帧数据从共享缓冲器中读取而不是从共享缓冲器中读取的一个监视周期，其中尚未从共享缓冲器读取帧数据的地址空间， 至少在检测到监视周期期间已经执行了帧数据的写入。 在下一个监视周期中，地址空间作为共享缓冲区的空闲地址释放。

公开(公告)号：US4851885A

公开(公告)日：1989-07-25

申请号：US147436

申请日：1988-01-25

申请人： Hiroshi Kurosaki

发明人： Hiroshi Kurosaki

IPC分类号： B65H31/24 ,  G03B27/62 ,  G03G15/00

CPC分类号： G03G15/60 ,  G03B27/6264 ,  G03G2215/00185 ,  G03G2215/0035

摘要： A control mechanism of an automatic document feeder for an electrophotographic copying machine is provided with a plurality of document discharge trays and a selecting device to select one of the document discharge trays to receive a document which has been processed and discharged. The control mechanism generally selects a specified one of the document discharge trays when documents are set on a supply tray and transported sequentially by the feeder. Only while the first of these documents is being transported from the supply tray into a processing position, however, the control mechanism selects a tray other than the specified one such that a document which may have been left inadvertently in the feeder by the previous user does not become mixed with the documents which are discharged subsequently.

摘要翻译： 一种用于电子照相复印机的自动文件馈送器的控制机构设置有多个原稿排出托盘和选择装置，用于选择一个文件排出托盘以接收已经被处理和排出的文档。 当文件设置在供应托盘上并由进料器依次传送时，控制机构通常选择指定的一个原稿排出托盘。 然而，只有当这些文件中的第一个从供应托盘运送到处理位置时，控制机构选择除指定的托盘之外的托盘，使得可能由先前用户在进纸器中不经意地遗留的文档 不会随后被释放的文件混合在一起。

公开(公告)号：US08189589B2

公开(公告)日：2012-05-29

申请号：US12405393

申请日：2009-03-17

申请人： Jun Tanaka ,  Hiroshi Tomonaga ,  Takashi Kuwabara ,  Hiroshi Kurosaki

发明人： Jun Tanaka ,  Hiroshi Tomonaga ,  Takashi Kuwabara ,  Hiroshi Kurosaki

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L45/22 ,  H04L41/0659 ,  H04L45/28 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/351 ,  H04L49/557

摘要： An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

摘要翻译： 一种装置包括输入部分，多个输出部分和切换部分。 输入部分输入分组，构建至少一个转发数据块，该转发数据块包括预定的目的地标识符和从输入的分组提取的分组数据。 切换部分包括转发目的地存储部分，用于与预定的目的地标识符相关联地存储识别多个输出部分之一的转发目的地标识符，并从输入部分接收至少一个转发数据块，并将其转发 基于转发目的地存储部分，响应于多个输出部分的操作状态的改变来更新多个输出部分中的一个输出部分。

公开(公告)号：US20100046534A1

公开(公告)日：2010-02-25

申请号：US12545899

申请日：2009-08-24

申请人： Hiroshi KUROSAKI ,  Satoshi Nemoto ,  Hideo Abe

发明人： Hiroshi KUROSAKI ,  Satoshi Nemoto ,  Hideo Abe

IPC分类号： H04L12/56

CPC分类号： H04L49/552 ,  H04L47/50 ,  H04L49/1523 ,  H04L49/3072 ,  H04L49/90 ,  H04L49/9094

摘要： A data transmission apparatus includes an input interface; an output interface; and a first and second switch portions which are provided between the input interface and the output interface and which transfer a frame from the input interface to a destination output interface, wherein the first and the second switch portions each include a buffer which stores the frame from the input interface according to the destination output interface, a scheduler which reads the frame from the buffer and transfers the frame to the destination output interface, and a frame amount detection portion which detects the amount of frames held in the buffer according to the destination output interface, and the scheduler controls reading from the buffer based on difference between the held frame amount of the first switch portion and the held frame amount of the second switch portion which is detected by the frame amount detection portion.

摘要翻译： 数据传输装置包括输入接口; 输出接口; 以及第一和第二开关部分，其设置在所述输入接口和所述输出接口之间，并且将帧从所述输入接口传送到目的地输出接口，其中所述第一和第二开关部分各自包括缓冲器，所述缓冲器存储来自 根据目的地输出接口的输入接口，从缓冲器读取帧并将帧传送到目的地输出接口的调度器，以及根据目的地输出检测保存在缓冲器中的帧量的帧量检测部分 接口，并且调度器基于由第一开关部分的保持帧量和由帧量检测部分检测到的第二开关部分的保持帧量之间的差异来控制从缓冲器的读取。

公开(公告)号：US06314536B1

公开(公告)日：2001-11-06

申请号：US09314652

申请日：1999-05-19

申请人： Hiroshi Kurosaki

发明人： Hiroshi Kurosaki

IPC分类号： G11C2900

CPC分类号： G11C7/1066 ,  G11C29/56

摘要： There is provided a memory testing apparatus capable of applying two address signals to a failure analysis memory in one test period, in the case that a memory under test operates in burst mode and adopts double data rate system. There is provided a burst address producing circuit 8 capable of producing two burst address signals in one test period, which comprises a clock-repetition-rate doubling circuit 15 for outputting a clock at twice the pulse repetition rate of the test period signal TI, a first multiplexer 16 for selecting either one of the clock TI and the rate-doubled clock from the circuit 15, and a burst address generating circuit for generating an address signal to be supplied to the failure analysis memory 5. The burst address generating circuit outputs two burst address signals in one test period by computing operation using an address signal first supplied from the pattern generator 2, in the case that a memory under test operates in burst mode and adopts double data rate system, and supplies them to the failure memory as burst address signals.

摘要翻译： 在一个测试周期内，提供一种能够在故障分析存储器中应用两个地址信号的存储器测试装置，在被测存储器以突发模式工作并采用双倍数据速率系统的情况下。 提供了一个能够在一个测试周期中产生两个突发地址信号的脉冲串地址产生电路8，该电路包括一个用于以测试周期信号TI的脉冲重复频率的两倍输出时钟的时钟重复倍增电路15， 第一多路复用器16，用于从电路15选择时钟TI和速率倍增时钟之一，以及用于产生要提供给故障分析存储器5的地址信号的脉冲串地址发生电路。脉冲串地址发生电路输出两个 在被测存储器以突发模式工作并采用双倍数据速率系统的情况下，通过使用首先从模式发生器2提供的地址信号计算操作的一个测试周期中的突发地址信号，并将其作为突发提供给故障存储器 地址信号

公开(公告)号：US07965093B2

公开(公告)日：2011-06-21

申请号：US12370609

申请日：2009-02-13

申请人： Tadahiko Baba ,  Hiroshi Kurosaki

发明人： Tadahiko Baba ,  Hiroshi Kurosaki

IPC分类号： G01R31/02 ,  G01R31/14

CPC分类号： G01R31/31937 ,  G01R31/31922

摘要： Provided is a test apparatus for testing a device under test, including a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals, a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe, and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

摘要翻译： 提供了一种用于测试被测设备的测试装置，包括：多选通产生部分，用于针对每个规定的测试周期产生包括以预定时间间隔布置的多个选通的多选通信号;数据检测部分， 根据每个选通脉冲，由被测器件输出的响应信号的逻辑值，以及数据宽度检测部分，其基于以下步骤检测响应信号的逻辑值与规定的期望值相匹配的期间的数据宽度 由数据检测部分输出的逻辑值的每个变化点。

公开(公告)号：US20060126517A1

公开(公告)日：2006-06-15

申请号：US11093973

申请日：2005-03-30

申请人： Hiroshi Kurosaki ,  Sugai Hidenori ,  Koyanagi Toshinori

发明人： Hiroshi Kurosaki ,  Sugai Hidenori ,  Koyanagi Toshinori

IPC分类号： H04L12/26 ,  H04L1/00 ,  H04J1/16

CPC分类号： H04L45/18 ,  H04L49/555

摘要： For providing a loop detection method and device which enables a general L2 switch to be applied and complicated condition equations or the like for determining a loop generation, a terminal moving state in which packets of a same transmitting source address are inputted to different ports is detected; a frequency of detecting the terminal moving state is counted for each port; and, when the frequency exceeds a threshold, it is regarded that a loop has occurred at the port.

摘要翻译： 为了提供使得能够应用通用L2开关的环路检测方法和装置以及用于确定循环生成的复杂条件方程等，检测到相同发送源地址的分组被输入到不同端口的终端移动状态 ; 对每个端口计数检测终端移动状态的频率; 并且当频率超过阈值时，认为在端口已经发生了循环。

公开(公告)号：US20100207650A1

公开(公告)日：2010-08-19

申请号：US12370609

申请日：2009-02-13

申请人： TADAHIKO BABA ,  HIROSHI KUROSAKI

发明人： TADAHIKO BABA ,  HIROSHI KUROSAKI

IPC分类号： G01R31/02 ,  G01R31/14

CPC分类号： G01R31/31937 ,  G01R31/31922

摘要： Provided is a test apparatus for testing a device under test, comprising a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals; a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe; and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

摘要翻译： 提供了一种用于测试被测器件的测试装置，包括：多选通产生部分，用于在每个规定的测试周期产生包括以预定时间间隔布置的多个选通的多次选通; 数据检测部分，根据每个选通信号，检测被被测设备输出的响应信号的逻辑值; 以及数据宽度检测部，其基于由数据检测部输出的逻辑值的每个变化点来检测表示响应信号的逻辑值与规定的期望值相匹配的期间的数据宽度。