公开(公告)号：US20080225612A1

公开(公告)日：2008-09-18

申请号：US12046783

申请日：2008-03-12

Applicant: Hiroyuki SUGAMOTO

Inventor： Hiroyuki SUGAMOTO

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/227

Abstract: According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to be connected to the memory cell and a replica word line are connected, the semiconductor memory device comprising: a write control signal generating unit that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal generated in response to a driving signal for driving the replica word line, the write control signal generating unit generating a write control signal to determine a data write time required to write data in the memory cell based on the replica word line activating signal.

Abstract translation: 根据一个实施例的一个方面，提供了半导体存储器件，通过读取具有等效于位线的负载的复制位线的复制单元来确定从存储器单元读取数据所需的数据读取时间 连接到存储器单元并且复制字线被连接，所述半导体存储器件包括：写入控制信号生成单元，其包括以多级耦合的逻辑门，用于接收响应于所述存储单元生成的复制字线激活信号的输入 用于驱动复制字线的驱动信号，写入控制信号产生单元产生写入控制信号，以基于复制字线激活信号确定在存储器单元中写入数据所需的数据写入时间。

公开(公告)号：US06525975B2

公开(公告)日：2003-02-25

申请号：US09947459

申请日：2001-09-07

Applicant: Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

Inventor： Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

IPC: G11C700

CPC classification number: G11C7/22 ,  G11C11/4076

Abstract: There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1. Through a decode circuit, a resultant signal is outputted as switch signal CL, or CLM.

公开(公告)号：US20080204067A1

公开(公告)日：2008-08-28

申请号：US12112782

申请日：2008-04-30

Applicant: Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

Inventor： Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

IPC: G01R31/28 ,  G11C29/00

CPC classification number: G11C8/08 ,  G01R31/31701 ,  G11C29/34

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract translation: 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

公开(公告)号：US07378863B2

公开(公告)日：2008-05-27

申请号：US11014789

申请日：2004-12-20

Applicant: Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Ogawa

Inventor： Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Ogawa

IPC: G01R31/28

CPC classification number: G11C8/08 ,  G01R31/31701 ,  G11C29/34

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract translation: 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

公开(公告)号：US06400618B1

公开(公告)日：2002-06-04

申请号：US09722472

申请日：2000-11-28

Applicant: Toshikazu Nakamura ,  Yoshinori Okajima ,  Hiroyuki Sugamoto

Inventor： Toshikazu Nakamura ,  Yoshinori Okajima ,  Hiroyuki Sugamoto

IPC: G11C700

CPC classification number: G11C29/785 ,  G11C29/808 ,  G11C29/848

Abstract: A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.

Abstract translation: 一种半导体存储器件，包括指示行方向上的缺陷部分的熔丝电路，并且还指示列方向上的缺陷部分，以及控制电路，其切换数据总线以避免列方向上指示的缺陷部分 当由熔丝电路在行方向指示的缺陷部分对应于输入到半导体存储器件的行地址时的熔丝电路。

公开(公告)号：US5349219A

公开(公告)日：1994-09-20

申请号：US175674

申请日：1993-12-30

Applicant: Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hidenori Nomura ,  Hiroyuki Sugamoto

Inventor： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hidenori Nomura ,  Hiroyuki Sugamoto

IPC: H01L27/02 ,  H01L27/10 ,  H01L27/15

CPC classification number: H01L27/0207

Abstract: A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.

Abstract translation: 晶片级半导体集成电路器件包括晶片，形成在晶片上的多个芯片，每个芯片具有内部逻辑电路，互连芯片的互连线以及与芯片之间的芯片耦合的钳位电路 其位于芯片的布置的周边，并且防止与位于周边的芯片相关的互连线处于浮置状态。

公开(公告)号：US5032889A

公开(公告)日：1991-07-16

申请号：US585515

申请日：1990-09-20

Applicant: Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hiroyuki Sugamoto ,  Hidenori Nomura

Inventor： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hiroyuki Sugamoto ,  Hidenori Nomura

IPC: H01L21/3205 ,  H01L23/52 ,  H01L23/528

CPC classification number: H01L23/5286 ,  H01L23/52 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.

公开(公告)号：US09236097B2

公开(公告)日：2016-01-12

申请号：US13620184

申请日：2012-09-14

Applicant: Hiroyuki Sugamoto

Inventor： Hiroyuki Sugamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227

Abstract: A semiconductor memory device includes two memory cell arrays, a sense amplifier shared by the two memory cell arrays; and a control circuit configured to control data readout from the two memory cell arrays. Each memory cell array includes word lines, two or more bit lines, a dummy word line, memory cells provided at intersections of the bit lines and the word lines, and dummy cells provided at intersections of selected bit lines and the dummy word line. When the control circuit reads data from one memory cell array, the control circuit activates the dummy word line included in the other memory cell array and generates, with the dummy cell included in the other memory cell array, a reference level of the sense amplifier.

Abstract translation: 半导体存储器件包括两个存储单元阵列，由两个存储单元阵列共享的读出放大器; 以及控制电路，被配置为控制从两个存储单元阵列读出的数据。 每个存储单元阵列包括字线，两个或多个位线，虚拟字线，位线和字线的交点处提供的存储单元，以及设置在所选位线和虚拟字线的交点处的虚设单元。 当控制电路从一个存储单元阵列读取数据时，控制电路激活包含在另一个存储单元阵列中的虚拟字线，并且在其它存储单元阵列中包括的虚拟单元产生读出放大器的基准电平。

公开(公告)号：US06559669B2

公开(公告)日：2003-05-06

申请号：US09820715

申请日：2001-03-30

Applicant: Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Tanaka

Inventor： Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Tanaka

IPC: G01R3128

CPC classification number: G11C8/08 ,  G01R31/31701 ,  G11C29/34

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

公开(公告)号：US20100052727A1

公开(公告)日：2010-03-04

申请号：US12614713

申请日：2009-11-09

Applicant: Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

Inventor： Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

IPC: G01R31/28

CPC classification number: G11C8/08 ,  G01R31/31701 ,  G11C29/34

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract translation: 本发明提供一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地进行老化应力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号重新发出。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。