Semiconductor memory device with efficient redundancy operation
    1.
    发明授权
    Semiconductor memory device with efficient redundancy operation 失效
    半导体存储器件具有高效的冗余操作

    公开(公告)号:US06400618B1

    公开(公告)日:2002-06-04

    申请号:US09722472

    申请日:2000-11-28

    IPC分类号: G11C700

    摘要: A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.

    摘要翻译: 一种半导体存储器件,包括指示行方向上的缺陷部分的熔丝电路,并且还指示列方向上的缺陷部分,以及控制电路,其切换数据总线以避免列方向上指示的缺陷部分 当由熔丝电路在行方向指示的缺陷部分对应于输入到半导体存储器件的行地址时的熔丝电路。

    Photocatalytic coating film and method for producing same
    4.
    发明授权
    Photocatalytic coating film and method for producing same 有权
    光催化涂膜及其制备方法

    公开(公告)号:US09517459B2

    公开(公告)日:2016-12-13

    申请号:US14124292

    申请日:2012-06-06

    摘要: Provided is a photocatalytic coating film that can develop excellent photocatalytic activity and exhibit superior adhesion to an adherend surface.The photocatalytic coating film is obtained by applying and drying a photocatalytic coating composition containing at least rod-like or needle-like titanium oxide particles and a binder component so that the photocatalytic coating film contains the titanium oxide particles in a content of 0.5 g/m2 or more. The photocatalytic coating film contains the titanium oxide particle in a content per unit volume (1 m2 by 1 μm thick) of less than 3.0 g. The titanium oxide particles preferably have an aspect ratio of 1.5 or more, the aspect ratio specified as the ratio of a long side length to a short side length of particle. The compositional ratio (by weight) of the titanium oxide particles to the binder component in the photocatalytic coating film is preferably from 1:6 to 30:1.

    摘要翻译: 通过涂布和干燥含有至少棒状或针状二氧化钛颗粒和粘合剂成分的光催化涂料组合物,使得光催化涂膜含有0.5g / m 2的氧化钛颗粒,得到光催化涂膜 或者更多。 光催化涂膜含有小于3.0g的每单位体积(1m 2×1μm)的氧化钛粒子。 优选氧化钛粒子的纵横比为1.5以上,纵横比规定为长边长与粒子的短边长的比例。 光催化性涂膜中的氧化钛粒子与粘合剂成分的组成比(重量比)优选为1:6〜30:1。

    Remote operation apparatus of working machine
    5.
    发明授权
    Remote operation apparatus of working machine 有权
    工作机远程操作装置

    公开(公告)号:US08922343B2

    公开(公告)日:2014-12-30

    申请号:US12775722

    申请日:2010-05-07

    IPC分类号: G08C19/16 G08C17/00

    摘要: In a remote operation apparatus of a working machine including a working machine side transmission/reception unit (21) and a radio remote operation means (3) having a remote control side transmission/reception unit (31), an ON/OFF control circuit (32) for controlling the operation/non-operation state of the remote control side transmission/reception unit (31) is disposed to the radio remote operation means (3), and the working machine side transmission/reception unit (21) is called when the remote control side transmission/reception unit (31) is in an operating state by that the ON/OFF control circuit (32) is turned on, and the data showing the driving state of the working machine (1) is transmitted from the working machine side transmission/reception unit (21) to the remote control side transmission/reception unit (31) to thereby reduce an electric power consumption amount on the radio remote operation means (3).

    摘要翻译: 在具有工作机侧发送接收单元(21)的工作机的远程操作装置和具有遥控侧发送接收单元(31)的无线遥控单元(3)的ON / OFF控制电路( 32)用于控制遥控器侧发送/接收单元(31)的操作/非操作状态设置在无线电远程操作装置(3)上,并且当工作机侧发送/接收单元(21)被调用时 远程控制侧发送/接收单元(31)处于操作状态,ON / OFF控制电路(32)接通,并且显示工作机(1)的驱动状态的数据从工作 机侧发送接收部(21)发送到遥控侧发送接收部(31),能够减少无线遥控装置(3)的电力消耗量。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US07827463B2

    公开(公告)日:2010-11-02

    申请号:US11270533

    申请日:2005-11-10

    IPC分类号: H03M13/00

    摘要: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.

    摘要翻译: 在具有纠错功能的半导体存储器件中,保持一组数据位的一部分和基于该数据位组的一组奇偶校验位,其中数据位集合和 奇偶校验位构成用于纠错的代码,并且在突发写入操作中以前导写入周期写入存储器单元。 基于数据位组和/或奇偶校验位集合的部分,在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合,以及另一组数据位 在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。

    Memory with word-line driver circuit having leakage prevention transistor
    9.
    发明授权
    Memory with word-line driver circuit having leakage prevention transistor 有权
    具有防漏晶体管的字线驱动电路的存储器

    公开(公告)号:US07577054B2

    公开(公告)日:2009-08-18

    申请号:US11979237

    申请日:2007-10-31

    IPC分类号: G11C8/00

    摘要: In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node and a second node and each of which has a gate connected to a third node, the word line being connected to a connection node of the two transistors. A first voltage or a second voltage lower than the first voltage is then applied to the third node, and the first voltage or second voltage is applied to the first node. In addition, between the third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor having a gate applied with the first voltage or a voltage in the vicinity thereof.

    摘要翻译: 在具有布置在其相交位置处的多个字线和位线和存储单元的半导体存储器中,驱动字线的字驱动电路具有驱动PMOS晶体管和驱动NMOS晶体管,其串联连接在第一 节点和第二节点,并且每个节点具有连接到第三节点的栅极,所述字线连接到所述两个晶体管的连接节点。 然后将第一电压或低于第一电压的第二电压施加到第三节点,并且将第一电压或第二电压施加到第一节点。 此外,在驱动PMOS晶体管的第三节点和栅极之间,提供了具有施加有第一电压的栅极或其附近的电压的防漏NMOS晶体管。