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    Spread spectrum at phase lock loop (PLL) feedback path
    1.
    发明授权
    Spread spectrum at phase lock loop (PLL) feedback path 失效
    锁相环（PLL）反馈路径上的扩展频谱

    公开(公告)号：US06377646B1

    公开(公告)日：2002-04-23

    申请号：US09120536

    申请日：1998-07-21

    申请人： I-Teh Sha

    发明人： I-Teh Sha

    IPC分类号： H03D324

    CPC分类号： H03C3/0933 ,  H03C3/0925 ,  H03L7/0891 ,  H03L7/197

    摘要： A plurality of four bit modulation read only memory (ROM) codes are generated with a PLL feedback divider. The output of a single phase lock loop is modulated to spread the bandwidth of a synthesized clock signal. By spreading the bandwidth, the amplitude of the synthesized clock signal is decreased with respect to its fundamental and its harmonics. As a result of reducing the peak amplitudes, the radiated electromagnetic emission level is significantly lower. Input phase lock loop system data is received as to selected phase lock loop characteristics. A continuous FBD is selected, and a bandwidth and system stability calculation is performed. A state variable system is determined and a numerical model for programming by finite differences is developed. A best path is determined to produce output data and ROM code by a least squares error method.

    摘要翻译： 利用PLL反馈分频器产生多个四位调制只读存储器（ROM）代码。 调制单个锁相环的输出以扩展合成时钟信号的带宽。 通过扩展带宽，合成时钟信号的幅度相对于其基波和谐波而减小。 由于降低峰值振幅，辐射电磁辐射水平显着降低。 接收到相位锁定环路特性的输入锁相环系统数据。 选择连续FBD，执行带宽和系统稳定性计算。 确定状态变量系统，并开发用于通过有限差分进行编程的数值模型。 确定通过最小二乘法错误方法产生输出数据和ROM代码的最佳路径。

    False lock protection in a delay-locked loop (DLL)
    2.
    发明授权
    False lock protection in a delay-locked loop (DLL) 有权
    延迟锁定环（DLL）中的虚假锁定保护

    公开(公告)号：US07336112B1

    公开(公告)日：2008-02-26

    申请号：US11466078

    申请日：2006-08-21

    申请人： I-Teh Sha ,  LiFeng Zhang ,  HaiTao Sun ,  JingRong Li

    发明人： I-Teh Sha ,  LiFeng Zhang ,  HaiTao Sun ,  JingRong Li

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095

    摘要： A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Δt) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Δt) is shorter than a desired delay period.

    摘要翻译： 提供了延迟锁定环（DLL）以产生包括用于伪锁检测的组合逻辑的多个延迟时钟信号。 组合逻辑仅使用多个延迟时钟信号的子集来提供指示延迟周期（Deltat）长于期望的延迟周期的前向指示符。 组合逻辑进一步提供指示延迟周期（Deltat）比期望的延迟周期短的后指示符。

    FALSE LOCK PROTECTION IN A DELAY-LOCKED LOOP (DLL)
    3.
    发明申请
    FALSE LOCK PROTECTION IN A DELAY-LOCKED LOOP (DLL) 有权
    延迟锁定中的假锁定保护（DLL）

    公开(公告)号：US20080042703A1

    公开(公告)日：2008-02-21

    申请号：US11466078

    申请日：2006-08-21

    申请人： I-Teh SHA ,  LiFeng ZHANG ,  HaiTao SUN ,  JingRong LI

    发明人： I-Teh SHA ,  LiFeng ZHANG ,  HaiTao SUN ,  JingRong LI

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095

    摘要： A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Δt) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Δt) is shorter than a desired delay period.

    摘要翻译： 提供了延迟锁定环（DLL）以产生包括用于伪锁检测的组合逻辑的多个延迟时钟信号。 组合逻辑仅使用多个延迟时钟信号的子集来提供指示延迟周期（Deltat）长于期望的延迟周期的前向指示符。 组合逻辑进一步提供指示延迟周期（Deltat）比期望的延迟周期短的后指示符。

    Circuit and method for controlling a spread spectrum transition
    5.
    发明授权
    Circuit and method for controlling a spread spectrum transition 有权
    用于控制扩频转换的电路和方法

    公开(公告)号：US06850554B1

    公开(公告)日：2005-02-01

    申请号：US09436522

    申请日：1999-11-09

    申请人： I-Teh Sha ,  Kuang-Yu Chen ,  Albert Chen

    发明人： I-Teh Sha ,  Kuang-Yu Chen ,  Albert Chen

    IPC分类号： H03L7/089 ,  H03L7/193 ,  H04B1/707 ,  H04J13/00 ,  H03D1/04

    CPC分类号： H03L7/193 ,  H03L7/0891 ,  H04B1/707

    摘要： A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

    摘要翻译： 提出了一种用于控制扩频转换的电路和方法，包括第一电路和第二电路。 第一电路可以被配置为响应于（i）参考信号，（ii）扩频ROM代码序列和（iii）命令信号来产生时钟信号。 第二电路可以被配置为使命令信号与反馈信号同步。 可以根据预定的数学公式生成扩频ROM代码序列，并根据预定标准进行优化。

    Circuit and method for linear control of a spread spectrum transition
    6.
    发明授权
    Circuit and method for linear control of a spread spectrum transition 有权
    用于线性控制扩频转换的电路和方法

    公开(公告)号：US06553057B1

    公开(公告)日：2003-04-22

    申请号：US09436155

    申请日：1999-11-09

    申请人： I-Teh Sha ,  Albert Chen ,  Kuang-Yu Chen

    发明人： I-Teh Sha ,  Albert Chen ,  Kuang-Yu Chen

    IPC分类号： H04B169

    CPC分类号： H04B15/04 ,  H03L7/197 ,  H04B2215/064

    摘要： A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.

    摘要翻译： 一种扩频时钟发生器，包括扩频调制电路和控制电路。 扩频调制电路可以被配置为响应于（i）线性ROM码序列，（ii）扩频ROM代码序列和（iii）命令信号来产生时钟信号。 控制电路可以被配置为使命令信号与反馈信号同步。 可以通过预定的数学公式产生线性ROM码序列和扩频ROM码序列，并根据预定标准进行优化。

    Voltage control oscillator (VCO) with automatic gain control
    7.
    发明授权
    Voltage control oscillator (VCO) with automatic gain control 有权
    具有自动增益控制的压控振荡器（VCO）

    公开(公告)号：US06404294B1

    公开(公告)日：2002-06-11

    申请号：US09618706

    申请日：2000-07-18

    申请人： I-Teh Sha ,  Kuang-Yu Chen ,  Trung Tran

    发明人： I-Teh Sha ,  Kuang-Yu Chen ,  Trung Tran

    IPC分类号： H03B524

    CPC分类号： H03L7/197 ,  H03L7/0995 ,  H03L2207/06

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a frequency that varies in response to (i) a voltage signal and (ii) a load. The second circuit may be configured to generate the load by coupling one or more resistive devices to a reference node in response to a control signal.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为产生具有响应于（i）电压信号和（ii）负载而变化的频率的输出信号。 第二电路可以被配置为通过响应于控制信号将一个或多个电阻装置耦合到参考节点来产生负载。