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21 条记录 (耗时 0.034 秒)

    Circuit and method for controlling a spread spectrum transition
    2.
    发明授权
    Circuit and method for controlling a spread spectrum transition 有权
    用于控制扩频转换的电路和方法

    公开(公告)号：US06850554B1

    公开(公告)日：2005-02-01

    申请号：US09436522

    申请日：1999-11-09

    申请人： I-Teh Sha ,  Kuang-Yu Chen ,  Albert Chen

    发明人： I-Teh Sha ,  Kuang-Yu Chen ,  Albert Chen

    IPC分类号： H03L7/089 ,  H03L7/193 ,  H04B1/707 ,  H04J13/00 ,  H03D1/04

    CPC分类号： H03L7/193 ,  H03L7/0891 ,  H04B1/707

    摘要： A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

    摘要翻译： 提出了一种用于控制扩频转换的电路和方法，包括第一电路和第二电路。 第一电路可以被配置为响应于（i）参考信号，（ii）扩频ROM代码序列和（iii）命令信号来产生时钟信号。 第二电路可以被配置为使命令信号与反馈信号同步。 可以根据预定的数学公式生成扩频ROM代码序列，并根据预定标准进行优化。

    Circuit and method for linear control of a spread spectrum transition
    3.
    发明授权
    Circuit and method for linear control of a spread spectrum transition 有权
    用于线性控制扩频转换的电路和方法

    公开(公告)号：US06553057B1

    公开(公告)日：2003-04-22

    申请号：US09436155

    申请日：1999-11-09

    申请人： I-Teh Sha ,  Albert Chen ,  Kuang-Yu Chen

    发明人： I-Teh Sha ,  Albert Chen ,  Kuang-Yu Chen

    IPC分类号： H04B169

    CPC分类号： H04B15/04 ,  H03L7/197 ,  H04B2215/064

    摘要： A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.

    摘要翻译： 一种扩频时钟发生器，包括扩频调制电路和控制电路。 扩频调制电路可以被配置为响应于（i）线性ROM码序列，（ii）扩频ROM代码序列和（iii）命令信号来产生时钟信号。 控制电路可以被配置为使命令信号与反馈信号同步。 可以通过预定的数学公式产生线性ROM码序列和扩频ROM码序列，并根据预定标准进行优化。

    Voltage control oscillator (VCO) with automatic gain control
    4.
    发明授权
    Voltage control oscillator (VCO) with automatic gain control 有权
    具有自动增益控制的压控振荡器（VCO）

    公开(公告)号：US06404294B1

    公开(公告)日：2002-06-11

    申请号：US09618706

    申请日：2000-07-18

    申请人： I-Teh Sha ,  Kuang-Yu Chen ,  Trung Tran

    发明人： I-Teh Sha ,  Kuang-Yu Chen ,  Trung Tran

    IPC分类号： H03B524

    CPC分类号： H03L7/197 ,  H03L7/0995 ,  H03L2207/06

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a frequency that varies in response to (i) a voltage signal and (ii) a load. The second circuit may be configured to generate the load by coupling one or more resistive devices to a reference node in response to a control signal.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为产生具有响应于（i）电压信号和（ii）负载而变化的频率的输出信号。 第二电路可以被配置为通过响应于控制信号将一个或多个电阻装置耦合到参考节点来产生负载。

    Line driving circuit
    6.
    发明授权
    Line driving circuit 有权
    线路驱动电路

    公开(公告)号：US06882187B1

    公开(公告)日：2005-04-19

    申请号：US10628078

    申请日：2003-07-25

    申请人： Hyunbae Kim ,  Chen Yu Wang ,  Kuang-Yu Chen

    发明人： Hyunbae Kim ,  Chen Yu Wang ,  Kuang-Yu Chen

    IPC分类号： H03K17/16 ,  H03B1/00

    CPC分类号： H03K17/164

    摘要： A line driver and a method for driving a line are disclosed. The line driver includes a first current device configured to initiate a change in the state of the line and a second current device configured to substantially complete the change. The first current device provides a first current and the second current device provides a second current that is smaller than the first current.

    摘要翻译： 公开了一种线驱动器和驱动线的方法。 线路驱动器包括被配置为启动线路的状态的改变的第一当前设备和被配置为基本上完成该改变的第二当前设备。 第一电流器件提供第一电流，第二电流器件提供小于第一电流的第二电流。

    Reduced power output buffer
    7.
    发明申请
    Reduced power output buffer 有权

    公开(公告)号：US20080204070A1

    公开(公告)日：2008-08-28

    申请号：US12070374

    申请日：2008-02-15

    申请人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    发明人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

    Computer enclosure incorporating a latch
    8.
    发明授权
    Computer enclosure incorporating a latch 失效
    包含闩锁的电脑机箱

    公开(公告)号：US06273532B1

    公开(公告)日：2001-08-14

    申请号：US09513229

    申请日：2000-02-24

    申请人： Yun-Long Chen ,  Yu-Tai Liu ,  Kuang-Yu Chen ,  Alvin Liu

    发明人： Yun-Long Chen ,  Yu-Tai Liu ,  Kuang-Yu Chen ,  Alvin Liu

    IPC分类号： A47B8100

    CPC分类号： G06F1/181 ,  E05B17/208 ,  E05C3/04 ,  E05C3/043

    摘要： A computer enclosure comprises a chassis and a hood attached to the chassis. The chassis has a latch resiliently and pivotably attached thereto. The latch forms a protrusion and an ejector. The hood has a fixing tab defining a fixing hole for engagingly receiving the protrusion of the latch therein thereby fixing the hood to the chassis. The fixing tab forms a bent end for ejection by the ejector of the latch thereby detaching the hood from the chassis.

    摘要翻译： 计算机外壳包括底盘和连接到底盘的罩。 底盘具有弹性地并且可枢转地附接到其上的闩锁。 闩锁形成突起和喷射器。 罩具有限定用于接合地容纳闩锁的突出部的固定孔的固定突起，从而将罩固定到底架。 固定翼片形成弯曲的端部，用于通过闩锁的喷射器喷射，从而将罩从底盘分离。

    Reduced power output buffer
    9.
    发明授权
    Reduced power output buffer 有权
    减少功率输出缓冲器

    公开(公告)号：US08138785B2

    公开(公告)日：2012-03-20

    申请号：US12586288

    申请日：2009-09-18

    申请人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    发明人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018521

    摘要： A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

    摘要翻译： 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

    Reduced power output buffer
    10.
    发明申请
    Reduced power output buffer 有权
    减少功率输出缓冲器

    公开(公告)号：US20100148817A1

    公开(公告)日：2010-06-17

    申请号：US12586288

    申请日：2009-09-18

    申请人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    发明人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

    IPC分类号： H03K19/003 ,  H03K19/094

    CPC分类号： H03K19/018521

    摘要： A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

    摘要翻译： 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。