SRAM-compatible memory for correcting invalid output data using parity and method of driving the same
    2.
    发明授权
    SRAM-compatible memory for correcting invalid output data using parity and method of driving the same 失效
    SRAM兼容存储器,用于校正使用奇偶校验的无效输出数据及其驱动方法

    公开(公告)号:US07165206B2

    公开(公告)日:2007-01-16

    申请号:US10659115

    申请日:2003-09-10

    CPC classification number: G11C11/40615 G11C11/406 G11C2211/4062

    Abstract: Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respectively. When invalid data is output from a specific memory bank due to the performance of a refresh operation or other factors, the invalid data are corrected by a data corrector using the parity value written in the parity bank, thus generating output data having the same logic value as the input data. The SRAM-compatible memory prevents a reduction in operation speed due to an internal operation, such as a refresh operation.

    Abstract translation: 这里公开了一种用于使用奇偶校验来校正无效输出数据的SRAM兼容存储器及其驱动方法。 在SRAM兼容存储器中,输入数据和从输入数据获得的奇偶校验值分别写入数据库和奇偶校验库。 当由于执行刷新操作或其他因素而从特定存储体输出无效数据时,使用写在奇偶校验库中的奇偶校验值由数据校正器校正无效数据,从而产生具有相同逻辑值的输出数据 作为输入数据。 SRAM兼容的存储器防止由于诸如刷新操作的内部操作而导致的操作速度的降低。

    Method for manufacturing light emitting displays and light emitting display device
    4.
    发明申请
    Method for manufacturing light emitting displays and light emitting display device 有权
    制造发光显示器和发光显示装置的方法

    公开(公告)号:US20080157651A1

    公开(公告)日:2008-07-03

    申请号:US11984690

    申请日:2007-11-20

    CPC classification number: H01J9/268 H01J9/261 H01J9/38

    Abstract: A method for manufacturing light emitting devices is provided. The method may reduce the inner pressure of a laminated image emitting device panel, thereby preventing failure of the panel. The method includes holding a first substrate with a lower chuck located in a vacuum chamber; holding a second substrate with an upper chuck located opposite the first chuck in the vacuum chamber; creating a high vacuum in the vacuum chamber; correcting positions of the first substrate and the second substrate; supplying gas having a temperature of about 50 to about 200° C. into the vacuum chamber; temporarily laminating the first substrate and the second substrate; venting the vacuum chamber; and bonding the first substrate and the second substrate. The panel is laminated after being filled with a heated gas and thus, when it is exposed to room temperature, the mobility of the gas decreases while reducing its initial inner pressure, thereby preventing panel failure.

    Abstract translation: 提供一种制造发光器件的方法。 该方法可以降低层叠图像发射装置面板的内部压力,从而防止面板的故障。 该方法包括:保持具有位于真空室中的下卡盘的第一基板; 在所述真空室中保持具有与所述第一卡盘相对的上卡盘的第二基板; 在真空室中产生高真空; 校正第一基板和第二基板的位置; 将具有约50至约200℃的温度的气体供应到真空室中; 临时层叠第一基板和第二基板; 排空真空室; 以及接合所述第一基板和所述第二基板。 在填充加热气体之后层压板,因此当暴露于室温时,气体的迁移率降低,同时降低其初始内部压力,从而防止面板故障。

    SRAM-compatible memory device employing DRAM cells
    5.
    发明授权
    SRAM-compatible memory device employing DRAM cells 失效
    采用DRAM单元的SRAM兼容存储器件

    公开(公告)号:US06822920B2

    公开(公告)日:2004-11-23

    申请号:US10639922

    申请日:2003-08-12

    CPC classification number: G11C11/40615 G11C11/406 G11C2211/4061

    Abstract: Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period “n” times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.

    Abstract translation: 这里公开了使用DRAM单元的同步SRAM兼容存储器。 在本发明的同步SRAM兼容存储器中,响应于具有基准时钟信号的周期的周期“n”的刷新时钟信号来控制刷新操作。 在芯片使能信号/ CS被激活时执行刷新操作。 响应于在芯片使能信号/ CS被激活时产生的写入/读取命令执行写入/读取访问操作。 因此,在本发明的同步SRAM兼容存储器的写/读访问操作中,不会由于DRAM单元的刷新操作而发生时间延迟。

    Circuit for plug/play in peripheral component interconnect bus
    6.
    发明授权
    Circuit for plug/play in peripheral component interconnect bus 失效
    外设组件互连总线插拔电路

    公开(公告)号:US5734841A

    公开(公告)日:1998-03-31

    申请号:US668362

    申请日:1996-06-26

    CPC classification number: G06F13/423

    Abstract: A circuit or plug/play (P/P) in a PCI bus which can store information in a PCI master/target device so that an address input board or component installed in a PCI local bus necessary for developing an information processing system adopting the PCI bus can support complete automatic, the circuit including controlling means for generating a plurality of latch enabling signals having a predetermined delay time, in accordance with a PCI reset signal, a clock signal and an address signal for reading data, input generating means having a plurality of input generating blocks and generating a plurality of data to be written in corresponding latches, in accordance with the PCI reset signal, data latching means having a plurality of latches, constituted by a plurality of latch groups corresponding to the plurality of input generating blocks, for writing data applied from the input generating means, in accordance with the latch enabling signals from the controlling means; and a PCI interface for reading and outputting corresponding data written in the respective latch groups in the latching means, in accordance with the address signal for reading externally supplied data.

    Abstract translation: PCI总线中的电路或插头/播放(P / P),其可以将信息存储在PCI主/目标设备中,以便安装在PCI本地总线中的地址输入板或组件用于开发采用PCI的信息处理系统 总线可以支持完全自动,该电路包括用于根据PCI复位信号,时钟信号和用于读取数据的地址信号产生具有预定延迟时间的多个锁存使能信号的控制装置,具有多个 根据PCI复位信号生成要写入相应锁存器的多个数据,具有多个锁存器的数据锁存装置由与多个输入产生块对应的多个锁存器组构成, 用于根据来自控制装置的锁存使能信号写入从输入产生装置施加的数据; 以及PCI接口,用于根据用于读取外部提供的数据的地址信号读取和输出写入锁存装置中的相应锁存组中的相应数据。

    METHOD FOR MANUFACTURING LIGHT EMITTING DISPLAYS AND LIGHT EMITTING DISPLAY DEVICE
    8.
    发明申请
    METHOD FOR MANUFACTURING LIGHT EMITTING DISPLAYS AND LIGHT EMITTING DISPLAY DEVICE 有权
    用于制造发光显示器和发光显示装置的方法

    公开(公告)号:US20110168333A1

    公开(公告)日:2011-07-14

    申请号:US13053829

    申请日:2011-03-22

    CPC classification number: H01J9/268 H01J9/261 H01J9/38

    Abstract: A method for manufacturing light emitting devices is provided. The method may reduce the inner pressure of a laminated image emitting device panel, thereby preventing failure of the panel. The method includes holding a first substrate with a lower chuck located in a vacuum chamber; holding a second substrate with an upper chuck located opposite the first chuck in the vacuum chamber; creating a high vacuum in the vacuum chamber; correcting positions of the first substrate and the second substrate; supplying gas having a temperature of about 50 to about 200° C. into the vacuum chamber; temporarily laminating the first substrate and the second substrate; venting the vacuum chamber; and bonding the first substrate and the second substrate. The panel is laminated after being filled with a heated gas and thus, when it is exposed to room temperature, the mobility of the gas decreases while reducing its initial inner pressure, thereby preventing panel failure.

    Abstract translation: 提供一种制造发光器件的方法。 该方法可以降低层叠图像发射装置面板的内部压力,从而防止面板的故障。 该方法包括:保持具有位于真空室中的下卡盘的第一基板; 在所述真空室中保持具有与所述第一卡盘相对的上卡盘的第二基板; 在真空室中产生高真空; 校正第一基板和第二基板的位置; 将具有约50至约200℃的温度的气体供应到真空室中; 临时层叠第一基板和第二基板; 排空真空室; 以及接合所述第一基板和所述第二基板。 在填充加热气体之后层压板,因此当暴露于室温时,气体的迁移率降低,同时降低其初始内部压力,从而防止面板故障。

    Method for manufacturing light emitting displays and light emitting display device
    9.
    发明授权
    Method for manufacturing light emitting displays and light emitting display device 有权
    制造发光显示器和发光显示装置的方法

    公开(公告)号:US07931772B2

    公开(公告)日:2011-04-26

    申请号:US11984690

    申请日:2007-11-20

    CPC classification number: H01J9/268 H01J9/261 H01J9/38

    Abstract: A method for manufacturing light emitting devices is provided. The method may reduce the inner pressure of a laminated image emitting device panel, thereby preventing failure of the panel. The method includes holding a first substrate with a lower chuck located in a vacuum chamber; holding a second substrate with an upper chuck located opposite the first chuck in the vacuum chamber; creating a high vacuum in the vacuum chamber; correcting positions of the first substrate and the second substrate; supplying gas having a temperature of about 50 to about 200° C. into the vacuum chamber; temporarily laminating the first substrate and the second substrate; venting the vacuum chamber; and bonding the first substrate and the second substrate. The panel is laminated after being filled with a heated gas and thus, when it is exposed to room temperature, the mobility of the gas decreases while reducing its initial inner pressure, thereby preventing panel failure.

    Abstract translation: 提供一种制造发光器件的方法。 该方法可以降低层叠图像发射装置面板的内部压力,从而防止面板的故障。 该方法包括:保持具有位于真空室中的下卡盘的第一基板; 在所述真空室中保持具有与所述第一卡盘相对的上卡盘的第二基板; 在真空室中产生高真空; 校正第一基板和第二基板的位置; 将具有约50至约200℃的温度的气体供应到真空室中; 临时层叠第一基板和第二基板; 排空真空室; 以及接合所述第一基板和所述第二基板。 在填充加热气体之后层压板,因此当暴露于室温时,气体的迁移率降低,同时降低其初始内部压力,从而防止面板故障。

    Synchronous SRAM-compatible memory device including DRAM array with internal refresh
    10.
    发明授权
    Synchronous SRAM-compatible memory device including DRAM array with internal refresh 有权
    同步SRAM兼容存储器件,包括具有内部刷新的DRAM阵列

    公开(公告)号:US06847573B2

    公开(公告)日:2005-01-25

    申请号:US10608719

    申请日:2003-06-26

    CPC classification number: G11C11/40615 G11C7/1027 G11C7/1072 G11C11/406

    Abstract: The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh control unit. The data input/output unit controls input and output of data. The address input unit inputs a row address and a column address. The burst address generating unit generates a sequentially varying burst address. The state control unit generates a burst enable signal that enables the burst address generating unit, controls the data input/output unit, and generates a wait indication signal while an access operation of a previous frame is performed with respect to the memory array. The refresh timer generates a refresh request signal activated at regular intervals. The refresh control unit controls the refresh operation with respect to the DRAM array in response to the refresh request signal.

    Abstract translation: 同步SRAM兼容存储器包括DRAM阵列,数据输入/输出单元,地址输入单元,脉冲串地址生成单元,状态控制单元,刷新定时器和刷新控制单元。 数据输入/输出单元控制数据的输入和输出。 地址输入单元输入行地址和列地址。 突发地址生成单元生成顺序变化的突发地址。 状态控制单元产生使能脉冲串地址生成单元的脉冲串使能信号,控制数据输入/输出单元,并且在相对于存储器阵列执行先前帧的访问操作时产生等待指示信号。 刷新定时器产生定期激活的刷新请求信号。 刷新控制单元响应于刷新请求信号控制相对于DRAM阵列的刷新操作。

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