公开(公告)号：US07165206B2

公开(公告)日：2007-01-16

申请号：US10659115

申请日：2003-09-10

申请人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

发明人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

IPC分类号： G11C29/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4062

摘要： Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respectively. When invalid data is output from a specific memory bank due to the performance of a refresh operation or other factors, the invalid data are corrected by a data corrector using the parity value written in the parity bank, thus generating output data having the same logic value as the input data. The SRAM-compatible memory prevents a reduction in operation speed due to an internal operation, such as a refresh operation.

摘要翻译： 这里公开了一种用于使用奇偶校验来校正无效输出数据的SRAM兼容存储器及其驱动方法。 在SRAM兼容存储器中，输入数据和从输入数据获得的奇偶校验值分别写入数据库和奇偶校验库。 当由于执行刷新操作或其他因素而从特定存储体输出无效数据时，使用写在奇偶校验库中的奇偶校验值由数据校正器校正无效数据，从而产生具有相同逻辑值的输出数据 作为输入数据。 SRAM兼容的存储器防止由于诸如刷新操作的内部操作而导致的操作速度的降低。

公开(公告)号：US06822920B2

公开(公告)日：2004-11-23

申请号：US10639922

申请日：2003-08-12

申请人： In Sun Yoo ,  Sun Hyoung Lee ,  Dong Woo Shin

发明人： In Sun Yoo ,  Sun Hyoung Lee ,  Dong Woo Shin

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period “n” times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.

摘要翻译： 这里公开了使用DRAM单元的同步SRAM兼容存储器。 在本发明的同步SRAM兼容存储器中，响应于具有基准时钟信号的周期的周期“n”的刷新时钟信号来控制刷新操作。 在芯片使能信号/ CS被激活时执行刷新操作。 响应于在芯片使能信号/ CS被激活时产生的写入/读取命令执行写入/读取访问操作。 因此，在本发明的同步SRAM兼容存储器的写/读访问操作中，不会由于DRAM单元的刷新操作而发生时间延迟。

公开(公告)号：US07085882B2

公开(公告)日：2006-08-01

申请号：US10695532

申请日：2003-10-28

申请人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

发明人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

IPC分类号： G06F12/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40618 ,  G11C2211/4062

摘要： Disclosed herein are an SRAM-compatible memory and method of driving the SRAM-compatible memory. The SRAM-compatible memory has memory banks, a parity generator and a parity bank. The memory banks each store corresponding one of input data in its DRAM cells specified by an input address. The memory banks perform write operations independently such that when a refresh operation or a write operation for a previous frame is being performed with respect to DRAM cells of a certain memory bank, the write operation of the input data is independently performed with respect to the respective memory banks except for the certain memory bank. The parity generator generates a input parity determined based on the input data and a certain preset parity value. The parity bank stores the input parity.

摘要翻译： 这里公开了SRAM兼容存储器和驱动SRAM兼容存储器的方法。 SRAM兼容存储器具有存储体，奇偶校验发生器和奇偶校验库。 存储体每个存储由输入地址指定的其DRAM单元中的输入数据之一。 存储体独立地执行写入操作，使得当相对于某个存储体的DRAM单元执行针对先前帧的刷新操作或写入操作时，输入数据的写入操作相对于相应的 记忆库除了某个记忆库。 奇偶校验发生器产生基于输入数据和某个预设奇偶校验值确定的输入奇偶校验。 奇偶校验库存储输入奇偶校验。

公开(公告)号：US06847573B2

公开(公告)日：2005-01-25

申请号：US10608719

申请日：2003-06-26

申请人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

发明人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40615 ,  G11C7/1027 ,  G11C7/1072 ,  G11C11/406

摘要： The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh control unit. The data input/output unit controls input and output of data. The address input unit inputs a row address and a column address. The burst address generating unit generates a sequentially varying burst address. The state control unit generates a burst enable signal that enables the burst address generating unit, controls the data input/output unit, and generates a wait indication signal while an access operation of a previous frame is performed with respect to the memory array. The refresh timer generates a refresh request signal activated at regular intervals. The refresh control unit controls the refresh operation with respect to the DRAM array in response to the refresh request signal.

摘要翻译： 同步SRAM兼容存储器包括DRAM阵列，数据输入/输出单元，地址输入单元，脉冲串地址生成单元，状态控制单元，刷新定时器和刷新控制单元。 数据输入/输出单元控制数据的输入和输出。 地址输入单元输入行地址和列地址。 突发地址生成单元生成顺序变化的突发地址。 状态控制单元产生使能脉冲串地址生成单元的脉冲串使能信号，控制数据输入/输出单元，并且在相对于存储器阵列执行先前帧的访问操作时产生等待指示信号。 刷新定时器产生定期激活的刷新请求信号。 刷新控制单元响应于刷新请求信号控制相对于DRAM阵列的刷新操作。

公开(公告)号：US5734841A

公开(公告)日：1998-03-31

申请号：US668362

申请日：1996-06-26

申请人： Dong Woo Shin ,  In Sun Yoo

发明人： Dong Woo Shin ,  In Sun Yoo

IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/423

摘要： A circuit or plug/play (P/P) in a PCI bus which can store information in a PCI master/target device so that an address input board or component installed in a PCI local bus necessary for developing an information processing system adopting the PCI bus can support complete automatic, the circuit including controlling means for generating a plurality of latch enabling signals having a predetermined delay time, in accordance with a PCI reset signal, a clock signal and an address signal for reading data, input generating means having a plurality of input generating blocks and generating a plurality of data to be written in corresponding latches, in accordance with the PCI reset signal, data latching means having a plurality of latches, constituted by a plurality of latch groups corresponding to the plurality of input generating blocks, for writing data applied from the input generating means, in accordance with the latch enabling signals from the controlling means; and a PCI interface for reading and outputting corresponding data written in the respective latch groups in the latching means, in accordance with the address signal for reading externally supplied data.

摘要翻译： PCI总线中的电路或插头/播放（P / P），其可以将信息存储在PCI主/目标设备中，以便安装在PCI本地总线中的地址输入板或组件用于开发采用PCI的信息处理系统 总线可以支持完全自动，该电路包括用于根据PCI复位信号，时钟信号和用于读取数据的地址信号产生具有预定延迟时间的多个锁存使能信号的控制装置，具有多个 根据PCI复位信号生成要写入相应锁存器的多个数据，具有多个锁存器的数据锁存装置由与多个输入产生块对应的多个锁存器组构成， 用于根据来自控制装置的锁存使能信号写入从输入产生装置施加的数据; 以及PCI接口，用于根据用于读取外部提供的数据的地址信号读取和输出写入锁存装置中的相应锁存组中的相应数据。

公开(公告)号：US08388441B2

公开(公告)日：2013-03-05

申请号：US12957360

申请日：2010-11-30

申请人： Dong Woo Shin ,  Kee Chul Kim ,  Jae Hwang Lee ,  Young Hwan Kim ,  Kyu Ho Lee

发明人： Dong Woo Shin ,  Kee Chul Kim ,  Jae Hwang Lee ,  Young Hwan Kim ,  Kyu Ho Lee

IPC分类号： A63F9/24

CPC分类号： A63F13/71 ,  A63F13/335 ,  A63F13/352 ,  A63F13/75 ,  A63F2300/513 ,  A63F2300/535 ,  A63F2300/5586 ,  G06F21/57 ,  G06F2221/2109

摘要： Disclosed herein is a method for displaying information about the use of a hack tool in the online game. When a game IDentification (ID) is input, a client system accesses a security server, and requests and receives the number of times that one or more hack tools have been used for the game ID. The client system provides the game ID and the number of times that hack tools have been used to a game server so that the number of times that hack tools have been used is shared by one or more gamers who participate in the game provided by the game server. When the client system detects the use of a hack tool, the client system increases the number of times that hack tools have been used for the game ID by 1, and provides the number of times that hack tools have been used to the security server.

摘要翻译： 本文公开了一种用于在线游戏中显示关于使用黑客工具的信息的方法。 当输入游戏标识（ID）时，客户端系统访问安全服务器，并请求并接收一个或多个黑客工具已被用于游戏ID的次数。 客户端系统提供游戏ID和黑客工具已经被使用到游戏服务器的次数，以便使用黑客工具的次数由参与游戏提供的游戏的一个或多个玩家共享 服务器。 当客户端系统检测到使用黑客工具时，客户端系统将攻击工具的游戏ID的次数增加1，并将攻击工具的次数提供给安全服务器。

公开(公告)号：US20080003363A1

公开(公告)日：2008-01-03

申请号：US11589783

申请日：2006-10-31

申请人： Jong Jin Park ,  Sung Woong Kim ,  Dong Woo Shin ,  Sang Hoon Park

发明人： Jong Jin Park ,  Sung Woong Kim ,  Dong Woo Shin ,  Sang Hoon Park

IPC分类号： B05D5/00 ,  B05D3/02 ,  B05D1/02

CPC分类号： H05K1/097 ,  B05D1/185 ,  B22F1/0059 ,  B22F2998/00 ,  C03C17/007 ,  C03C2217/42 ,  C03C2217/445 ,  C03C2217/479 ,  C03C2218/33 ,  C09D11/30 ,  H05K2201/0239 ,  Y10T428/25 ,  Y10T428/256 ,  Y10T428/2991 ,  B22F1/0018

摘要： A printable metal nanoparticle having a self-assembled monolayer (SAM) composed of a compound containing a thiol (—SH), isocyanide (—CN), amino (—NH2), carboxylate (—COO) or phosphate group, as a linker, formed on the surface thereof, and a method for formation of a conductive pattern using the same are provided. The metal nanoparticles of an exemplary embodiment can be easily formed into a conductive film or pattern by a printing method, and the resulting film or pattern exhibits excellent conductivity which optimally may be adjusted if desired. Therefore, the resulting metal nanoparticles of can be used to advantage in the fields such as antistatic washable sticky mats, antistatic shoes, conductive polyurethane printer rollers, electromagnetic interference shielding materials, etc.

摘要翻译： 具有由含有硫醇（-SH），异氰化物（-CN），氨基（-NH 2），羧酸酯（-COO）的化合物组成的自组装单层（SAM）的可印刷金属纳米颗粒， 或磷酸酯基，作为其表面上形成的接头，并且提供了使用其形成导电图案的方法。 可以通过印刷方法将示例性实施方案的金属纳米颗粒容易地形成为导电膜或图案，并且所得到的膜或图案显示出优异的导电性，如果需要，其可最佳地调节。 因此，所得金属纳米粒子可用于抗静电可洗粘垫，抗静电鞋，导电聚氨酯打印辊，电磁干扰屏蔽材料等领域。

公开(公告)号：US08893341B2

公开(公告)日：2014-11-25

申请号：US12585243

申请日：2009-09-09

申请人： Chan Woo Park ,  Sang Ho Seo ,  Seok In Hong ,  Jae Won Lee ,  Do Yeon Kim ,  Dong Woo Shin

发明人： Chan Woo Park ,  Sang Ho Seo ,  Seok In Hong ,  Jae Won Lee ,  Do Yeon Kim ,  Dong Woo Shin

IPC分类号： D06F37/24 ,  D06F35/00 ,  D06F37/20

CPC分类号： D06F37/203 ,  D06F37/245

摘要： Disclosed are a washing machine and a method of controlling spin-drying of the washing machine. The method changes the acceleration gradient of the drum passing a resonance point, i.e., the resonance point passing gradient of the drum, when the imbalance of the laundry due to the excessive vibration of the tub is sensed when passing a resonance point region (generally within 100 RPM, approximately 50˜80 RPM, after the entry into the spin-drying cycle) in the spin-drying cycle. Thus the position of the balancer is changed according to the imbalance of the laundry.

摘要翻译： 公开了洗衣机和控制洗衣机的旋转干燥的方法。 该方法通过谐振点的加速度梯度，即当鼓通过谐振点区域（通常在 100rpm，进入旋转干燥循环后约为50〜80RPM）。 因此，平衡器的位置根据衣物的不平衡而改变。

公开(公告)号：US07923110B2

公开(公告)日：2011-04-12

申请号：US11653889

申请日：2007-01-17

申请人： Jong Jin Park ,  Dong Woo Shin ,  Sung Woong Kim

发明人： Jong Jin Park ,  Dong Woo Shin ,  Sung Woong Kim

IPC分类号： B32B5/16

CPC分类号： G03F7/0047 ,  B05D1/185 ,  C03C17/06 ,  H05K3/02 ,  H05K2201/0257 ,  H05K2203/0514 ,  Y10S977/777 ,  Y10S977/778 ,  Y10S977/779 ,  Y10T428/2991

摘要： A metal nanoparticle which is prepared by forming a self-assembled monolayer including a terminal reactive group on the surface thereof, and introducing a functional group capable of being removed by the action of an acid or an base into the terminal reactive group wherein the self-assembled monolayer is built up of a thiol, an isocyanide, an amine, a carboxylate or a phosphate compound having the terminal reactive group, or built up of a thiol, an isocyanide, an amine, a carboxylate or a phosphate compound having no terminal reactive group followed by introducing the terminal reactive group thereto; and a method for forming a conductive pattern using the same are provided. Since the metal nanoparticle of exemplary embodiments of the present invention can easily form a high conductive film or a high conductive pattern through photo-irradiation and photo-degradation and randomly regulate its conductivity when occasions demand, it can be advantageously applied to an antistatic washable sticky film, antistatic shoes, a conductive polyurethane printer roller, an electromagnetic interference shielding, and the like.

摘要翻译： 一种金属纳米颗粒，其通过在其表面上形成包括末端反应性基团的自组装单层并将能够通过酸或碱的作用除去的官能团引入末端反应性基团而制备， 组装的单层由硫醇，异氰化物，胺，羧酸酯或具有末端反应性基团的磷酸酯化合物构成，或由硫醇，异氰化物，胺，羧酸酯或不具有末端反应性的磷酸酯化合物 然后引入末端反应性基团; 并且提供了使用其形成导电图案的方法。 由于本发明的示例性实施方案的金属纳米颗粒可以通过光照射和光降解容易地形成高导电膜或高导电图案，并且当需要时随机调节其导电性，因此可以有利地应用于抗静电可洗粘性 薄膜，抗静电鞋，导电性聚氨酯打印辊，电磁干扰屏蔽等。

公开(公告)号：US06772359B2

公开(公告)日：2004-08-03

申请号：US09725896

申请日：2000-11-30

申请人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

发明人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

IPC分类号： G06F104

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C7/22 ,  G11C11/4076 ,  Y02D10/13 ,  Y02D10/14

摘要： A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.

摘要翻译： 提供了一种用于Rambus DRAM的时钟控制电路，其通过预先确定所应用的命令是读取还是当前控制命令来降低功耗，并且仅在读取或当前控制命令期间启用用于外部输出内部数据的时钟信号。 我们的电路包括：输入信号检测单元，用于当将所选择的Rambus DRAM的地址值与COLC分组的设备地址值进行比较的第一比较信号中的一个产生使能信号，以及第二比较信号， 所选择的具有COLX分组的设备地址值的Rambus DRAM被使能，并且当命令是读取或当前控制命令时; 信号产生单元，用于当所述第一和第二比较信号之一被使能时，产生用于外部输出内部数据的时钟使能信号; 输出信号维持单元，用于在读取或当前控制命令中输出用于将时钟使能信号保持到信号生成单元的控制信号; 以及输出信号控制单元，用于当命令不是读取或当前控制命令时，向信号生成单元输出用于控制产生时钟使能信号的控制信号。