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公开(公告)号：US20130315023A1
公开(公告)日：2013-11-28
申请号：US13586155
申请日：2012-08-15
Applicant: Jin Youp CHA , Jae Il KIM
Inventor： Jin Youp CHA , Jae Il KIM
IPC: G11C8/08
Abstract: A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.
Abstract translation: 列选择信号生成电路包括：第一电流控制器，被配置为响应于存储体活动信号来控制预列选择信号的电平，驱动器被配置为响应于预列选择产生放大列选择信号 信号和第二电流控制器，其被配置为响应于存储体有效信号而产生驱动器的输出信号作为列选择信号。
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公开(公告)号：US20130265101A1
公开(公告)日：2013-10-10
申请号：US13585972
申请日：2012-08-15
Applicant: Jin Youp CHA , Jae Il KIM
Inventor： Jin Youp CHA , Jae Il KIM
IPC: H01H85/04
Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.
Abstract translation: 反熔丝电路包括：反熔丝单元，其包括能够响应于破裂信号被编程的反熔丝，并且被配置为产生对应于反熔丝的状态的熔丝信号; 虚拟熔丝单元，其包括虚拟熔丝并且被配置为产生对应于所述虚拟熔丝的状态的虚拟熔丝信号; 以及阻挡单元，被配置为响应于所述虚拟熔丝信号的状态而将所述熔丝信号输出为熔丝输出信号。
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公开(公告)号：US08749298B2
公开(公告)日：2014-06-10
申请号：US13585972
申请日：2012-08-15
Applicant: Jin Youp Cha , Jae Il Kim
Inventor： Jin Youp Cha , Jae Il Kim
Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.
Abstract translation: 反熔丝电路包括：反熔丝单元，其包括能够响应于破裂信号被编程的反熔丝，并且被配置为产生对应于反熔丝的状态的熔丝信号; 虚拟熔丝单元，其包括虚拟熔丝并且被配置为产生对应于所述虚拟熔丝的状态的虚拟熔丝信号; 以及阻挡单元，被配置为响应于所述虚拟熔丝信号的状态而将所述熔丝信号输出为熔丝输出信号。
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公开(公告)号：US08717087B2
公开(公告)日：2014-05-06
申请号：US13589205
申请日：2012-08-20
Applicant: Jin Youp Cha , Jae Il Kim
Inventor： Jin Youp Cha , Jae Il Kim
IPC: H01H37/76
CPC classification number: G11C17/18 , G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/00
Abstract: An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.
Abstract translation: 反熔丝电路包括：破裂单元，包括在编程模式期间响应于输入断裂信号编程的反熔丝，并且被配置为产生对应于反熔丝的状态的输出断裂信号以输出所产生的输出 电压钳位单元，被配置为产生与外部电压电平成比例的钳位电压，以在外部电压电平上升到预定电平以上时生成具有恒定电压电平的钳位电压;以及熔丝信号 生成单元，被配置为在编程模式的初始阶段将传输节点复位为钳位电压，以在输出模式期间响应于传输节点的电压电平生成熔丝信号。
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公开(公告)号：US20130315007A1
公开(公告)日：2013-11-28
申请号：US13586047
申请日：2012-08-15
Applicant: Jin Youp CHA , Jae Il KIM
Inventor： Jin Youp CHA , Jae Il KIM
IPC: G11C29/00
CPC classification number: G11C29/40 , G11C29/34 , G11C2029/2602
Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
Abstract translation: 一种半导体存储装置，包括测试电路，该测试电路被配置为通过在第一测试模式期间比较和压缩存储在存储体内的多个存储单元中的数据来产生压缩数据，并且被配置为将压缩数据作为测试数据输出到输入/输出 在第一测试模式期间通过一个所选择的全局线填充测试电路，并且测试电路被配置为在第二测试模式期间将压缩数据发送到多个全局线路，在第二测试模式期间组合加载在各个全局线路中的压缩数据 并且在第二测试模式期间将组合结果作为测试数据输出到输入/输出焊盘。
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Patent Agency Ranking
公开(公告)号：US08358555B2
公开(公告)日：2013-01-22
申请号：US12835978
申请日：2010-07-14
Applicant: Jin Youp Cha , Jae Jin Lee
Inventor： Jin Youp Cha , Jae Jin Lee
CPC classification number: G11C17/16 , G11C29/785
Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.
Abstract translation: 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。
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公开(公告)号：US08867287B2
公开(公告)日：2014-10-21
申请号：US13586047
申请日：2012-08-15
Applicant: Jin Youp Cha , Jae Il Kim
Inventor： Jin Youp Cha , Jae Il Kim
CPC classification number: G11C29/40 , G11C29/34 , G11C2029/2602
Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
Abstract translation: 一种半导体存储装置，包括测试电路，该测试电路被配置为通过在第一测试模式期间比较和压缩存储在存储体内的多个存储单元中的数据来产生压缩数据，并且被配置为将压缩数据作为测试数据输出到输入/输出 在第一测试模式期间通过一个所选择的全局线填充测试电路，并且测试电路被配置为在第二测试模式期间将压缩数据发送到多个全局线路，在第二测试模式期间组合加载在各个全局线路中的压缩数据 并且在第二测试模式期间将组合结果作为测试数据输出到输入/输出焊盘。
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公开(公告)号：US08184496B2
公开(公告)日：2012-05-22
申请号：US12648317
申请日：2009-12-29
Applicant: Jin-Youp Cha , Sang-Jin Byun
Inventor： Jin-Youp Cha , Sang-Jin Byun
IPC: G11C17/16
CPC classification number: G11C29/785 , G11C17/16
Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.
Abstract translation: 半导体器件包括感测单元，其被配置为感测编程感测节点的值是否在预定范围内，连接到编程感测节点的熔丝，编程电压提供单元，其被配置为向编程感测节点提供编程电压， 以及传送单元，其被配置为响应于感测单元的感测结果传送编程感测节点的值。
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公开(公告)号：US08049544B2
公开(公告)日：2011-11-01
申请号：US12627179
申请日：2009-11-30
Applicant: Nam-Pyo Hong , Jin-Youp Cha
Inventor： Nam-Pyo Hong , Jin-Youp Cha
IPC: H03L7/06
CPC classification number: H03L7/0816 , G11C7/222 , H03L7/0814
Abstract: A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.
Abstract translation: 延迟锁定环电路包括：相位比较单元，被配置为将参考时钟与反馈时钟进行比较并输出相位比较信号;时钟延迟单元，被配置为响应于相位比较信号延迟第一参考时钟，以输出 第一延迟锁定时钟，根据频率信息信号延迟第一延迟锁定时钟和第二参考时钟之一，并输出第二延迟锁定时钟;延迟锁定时钟生成单元，被配置为输出延迟锁定时钟作为 第一延迟锁定时钟和第二延迟锁定时钟的相位混合时钟，第一延迟锁定时钟或响应于频率信息信号和延迟传递信号的第二延迟锁定时钟，以及延迟复制模型单元，被配置为 反映参考时钟的延迟状况。
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公开(公告)号：US20110158026A1
公开(公告)日：2011-06-30
申请号：US12835978
申请日：2010-07-14
Applicant: Jin Youp CHA , Jae Jin Lee
Inventor： Jin Youp CHA , Jae Jin Lee
IPC: G11C17/16
CPC classification number: G11C17/16 , G11C29/785
Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.
Abstract translation: 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。
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