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    COLUMN SELECT SIGNAL GENERATION CIRCUIT
    1.
    发明申请
    COLUMN SELECT SIGNAL GENERATION CIRCUIT 有权
    列选择信号生成电路

    公开(公告)号：US20130315023A1

    公开(公告)日：2013-11-28

    申请号：US13586155

    申请日：2012-08-15

    Applicant: Jin Youp CHA ,  Jae Il KIM

    Inventor： Jin Youp CHA ,  Jae Il KIM

    IPC: G11C8/08

    CPC classification number: G11C7/12 ,  G11C8/10

    Abstract: A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.

    Abstract translation: 列选择信号生成电路包括：第一电流控制器，被配置为响应于存储体活动信号来控制预列选择信号的电平，驱动器被配置为响应于预列选择产生放大列选择信号 信号和第二电流控制器，其被配置为响应于存储体有效信号而产生驱动器的输出信号作为列选择信号。

    ANTI-FUSE CIRCUIT
    2.
    发明申请
    ANTI-FUSE CIRCUIT 有权
    防冻电路

    公开(公告)号：US20130265101A1

    公开(公告)日：2013-10-10

    申请号：US13585972

    申请日：2012-08-15

    Applicant: Jin Youp CHA ,  Jae Il KIM

    Inventor： Jin Youp CHA ,  Jae Il KIM

    IPC: H01H85/04

    CPC classification number: G11C17/16 ,  G11C17/18

    Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

    Abstract translation: 反熔丝电路包括：反熔丝单元，其包括能够响应于破裂信号被编程的反熔丝，并且被配置为产生对应于反熔丝的状态的熔丝信号; 虚拟熔丝单元，其包括虚拟熔丝并且被配置为产生对应于所述虚拟熔丝的状态的虚拟熔丝信号; 以及阻挡单元，被配置为响应于所述虚拟熔丝信号的状态而将所述熔丝信号输出为熔丝输出信号。

    TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS
    3.
    发明申请
    TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS 有权
    测试电路和半导体存储器件的方法

    公开(公告)号：US20130315007A1

    公开(公告)日：2013-11-28

    申请号：US13586047

    申请日：2012-08-15

    Applicant: Jin Youp CHA ,  Jae Il KIM

    Inventor： Jin Youp CHA ,  Jae Il KIM

    IPC: G11C29/00

    CPC classification number: G11C29/40 ,  G11C29/34 ,  G11C2029/2602

    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

    Abstract translation: 一种半导体存储装置，包括测试电路，该测试电路被配置为通过在第一测试模式期间比较和压缩存储在存储体内的多个存储单元中的数据来产生压缩数据，并且被配置为将压缩数据作为测试数据输出到输入/输出 在第一测试模式期间通过一个所选择的全局线填充测试电路，并且测试电路被配置为在第二测试模式期间将压缩数据发送到多个全局线路，在第二测试模式期间组合加载在各个全局线路中的压缩数据 并且在第二测试模式期间将组合结果作为测试数据输出到输入/输出焊盘。

    ANTI-FUSE CIRCUIT
    4.
    发明申请
    ANTI-FUSE CIRCUIT 有权
    防冻电路

    公开(公告)号：US20130314149A1

    公开(公告)日：2013-11-28

    申请号：US13589205

    申请日：2012-08-20

    Applicant: Jin Youp CHA ,  Jae Il KIM

    Inventor： Jin Youp CHA ,  Jae Il KIM

    IPC: H01H85/04

    CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.

    Abstract translation: 反熔丝电路包括：破裂单元，包括在编程模式期间响应于输入断裂信号编程的反熔丝，并且被配置为产生对应于反熔丝的状态的输出断裂信号以输出所产生的输出 电压钳位单元，被配置为产生与外部电压电平成比例的钳位电压，以在外部电压电平上升到预定电平以上时生成具有恒定电压电平的钳位电压;以及熔丝信号 生成单元，被配置为在编程模式的初始阶段将传输节点复位为钳位电压，以在输出模式期间响应于传输节点的电压电平生成熔丝信号。

    TOUCH PANEL
    5.
    发明申请
    TOUCH PANEL 审中-公开
    触控面板

    公开(公告)号：US20120194482A1

    公开(公告)日：2012-08-02

    申请号：US13083418

    申请日：2011-04-08

    Applicant: Jae Il KIM ,  Jong Young LEE ,  Yong Soo OH

    Inventor： Jae Il KIM ,  Jong Young LEE ,  Yong Soo OH

    IPC: G06F3/042

    CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/045

    Abstract: Disclosed herein is a touch panel 100. The touch panel 100 according to the present invention includes: transparent electrode patterns 120 formed on a surface of a transparent substrate 110 and patterned to have opening portions 125; and a light guide 130 disposed on an outside of the transparent substrate 110, the light guide 130 passing only the lights within a predetermined angle from a vertical direction with respect to the surface of the transparent substrate 110, among the lights incident onto the transparent electrode patterns 120 and the opening portions 125 and the lights reflected from the transparent electrode patterns 120 and the opening portions 125. The present invention selectively passes the lights incident onto the transparent electrode patterns 120 and the opening portions 125 within specific angles by employing the light guide 130, thereby improving the visibility of the touch panel 100.

    Abstract translation: 这里公开了触摸面板100.根据本发明的触摸面板100包括：形成在透明基板110的表面上并且被图案化以具有开口部分125的透明电极图案120; 以及配置在透明基板110的外侧的导光体130，在入射到透明电极的光中，导光体130仅从相对于透明基板110的表面的垂直方向以预定角度通过预定角度的光 图案120和开口部分125以及从透明电极图案120和开口部分125反射的光。本发明通过采用导光体将特定角度中入射到透明电极图案120和开口部分125上的光选择性地通过 130，从而提高触摸面板100的可视性。

    TOUCH PANEL
    7.
    发明申请
    TOUCH PANEL 审中-公开
    触控面板

    公开(公告)号：US20110298728A1

    公开(公告)日：2011-12-08

    申请号：US12880986

    申请日：2010-09-13

    Applicant: Woon Chun Kim ,  Yong Soo Oh ,  Jong Young Lee ,  Jae Il KIM

    Inventor： Woon Chun Kim ,  Yong Soo Oh ,  Jong Young Lee ,  Jae Il KIM

    IPC: G06F3/041

    CPC classification number: G06F3/045 ,  G06F3/044

    Abstract: Disclosed herein is a touch panel 100 including: a transparent electrode 120 formed on one surface of a transparent substrate 110, a protective layer 130 formed at the side surface of the transparent electrode 120 so that its upper end 133 surrounds the edge of one surface of the transparent electrode 120 and its lower end 137 protrudes in the edge direction of the transparent substrate 110, and an electrode wiring 140 that is formed at the side surface of the protective layer 130 so as to surround the lower end 137 of the protective layer 130 protruding in the edge direction of the transparent substrate 110. The protective layer 130 is interposed between the transparent electrode 120 and the electrode wiring 140 to prevent the electromigration (EM).

    Abstract translation: 这里公开了一种触摸面板100，其包括：形成在透明基板110的一个表面上的透明电极120，形成在透明电极120的侧表面处的保护层130，使得其上端133包围一个表面的边缘 透明电极120及其下端137沿着透明基板110的边缘方向突出，并且形成在保护层130的侧表面处以围绕保护层130的下端137的电极布线140 在透明基板110的边缘方向上突出。保护层130介于透明电极120和电极布线140之间以防止电迁移（EM）。

    DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME
    8.
    发明申请
    DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME 审中-公开
    数据输入/输出电路和具有该数据输入/输出电路的半导体存储器

    公开(公告)号：US20110103156A1

    公开(公告)日：2011-05-05

    申请号：US12648997

    申请日：2009-12-29

    Applicant: Jae Il KIM ,  Jong Chern Lee

    Inventor： Jae Il KIM ,  Jong Chern Lee

    IPC: G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/1051 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1078 ,  G11C8/18 ,  G11C2207/002

    Abstract: A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation.

    Abstract translation: 数据输入/输出电路包括等级选择部分和数据输入/输出部分。 等级选择部分响应于芯片选择信号选择性地连接到第一和第二等级中的一个，并且将数据输出到连接的等级或从连接的等级接收数据。 在读取操作期间，数据输入/输出部分通过数据焊盘将从等级选择部分发送的数据输出到外部设备，并且在写入操作期间将输入到数据焊盘的数据输出到等级选择部分。

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