公开(公告)号：US08631366B2

公开(公告)日：2014-01-14

申请号：US12708242

申请日：2010-02-18

Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

Abstract translation: 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

公开(公告)号：US08495532B2

公开(公告)日：2013-07-23

申请号：US13076649

申请日：2011-03-31

Applicant: Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

Abstract translation: 一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。 通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。 技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

公开(公告)号：US08468470B2

公开(公告)日：2013-06-18

申请号：US13238127

申请日：2011-09-21

Applicant: Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.

Abstract translation: 一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接 图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

公开(公告)号：US08448120B2

公开(公告)日：2013-05-21

申请号：US13045839

申请日：2011-05-09

Applicant: Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract translation: 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US08327301B2

公开(公告)日：2012-12-04

申请号：US12616956

申请日：2009-11-12

Applicant: Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

Inventor： Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/00 ,  G03F7/70433 ,  G03F7/705 ,  G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: In a method of designing a double patterning mask set, a chip is first divided into a grid that includes grid cells. A metal layer of the chip is laid out. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first indicator, and all right-boundary patterns of the metal layer are assigned with a second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set. All patterns assigned with the first indicator are transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set.

Abstract translation: 在设计双重图案掩模组的方法中，首先将芯片划分成包括网格单元的网格。 布置芯片的金属层。 在基本上每个网格单元中，金属层的所有左边界图案被分配有第一指示符，并且金属层的所有右边界图案被分配有第二指示符。 从一行中的一个网格单元开始，指示符更改在整行中传播。 网格单元中的所有图案都转移到双重图案掩模集合。 分配有第一指示符的所有图案被转移到双重图案掩模组的第一掩模，并且分配有第二指示符的所有图案被转移到双重图案掩模组的第二掩模。

公开(公告)号：US20120288786A1

公开(公告)日：2012-11-15

申请号：US13045839

申请日：2011-05-09

Applicant: Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G03F1/00 ,  G06F17/50 ,  G03F7/20

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract translation: 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US20120254811A1

公开(公告)日：2012-10-04

申请号：US13076649

申请日：2011-03-31

Applicant: Ke-Ying SU ,  Ching-Shun YANG ,  Jui-Feng KUAN ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

Inventor： Ke-Ying SU ,  Ching-Shun YANG ,  Jui-Feng KUAN ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

Abstract translation: 一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。 通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。 技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

公开(公告)号：US20120226479A1

公开(公告)日：2012-09-06

申请号：US13039730

申请日：2011-03-03

Applicant: Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yung-Chin Hou

Inventor： Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yung-Chin Hou

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Abstract translation: 公开了一种产生电阻 - 电容（RC）技术文件的方法。 该方法包括从IC铸造接收多个金属方案并将多个金属方案分成一个或多个模块化RC组。 该方法还包括识别模块化RC结构; 通过场解算器计算模块RC结构的电容值; 基于不具有互连的各种互连层计算RC结构的等效介电常数和等效高度; 计算所述多个金属方案中的每一种的等效介电常数和等效高度; 以及从所述模块化RC结构的电容值导出所述多个金属方案中的每一个的电容值。

公开(公告)号：US08252489B2

公开(公告)日：2012-08-28

申请号：US13167905

申请日：2011-06-24

Applicant: Ke-Ying Su ,  Chung-Hsing Wang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Ke-Ying Su ,  Chung-Hsing Wang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G03F9/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5036

Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.

Abstract translation: 一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模 。 确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。 对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。 模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

公开(公告)号：US20120210279A1

公开(公告)日：2012-08-16

申请号：US13027520

申请日：2011-02-15

Applicant: Chin-Chang HSU ,  Wen-Ju YANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG ,  Lee-Chung LU

Inventor： Chin-Chang HSU ,  Wen-Ju YANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG ,  Lee-Chung LU

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract translation: 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。