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1.发明授权Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权集成电路结构解决深井等离子体充电问题及其形成方法公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译： 在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。 反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。
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公开(公告)号：US08929154B2
公开(公告)日：2015-01-06
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
发明人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/10 , G11C7/18 , H01L27/02 , G11C11/412 , G11C11/413 , H01L27/11
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译： 半导体结构包括第一带状电池，第一读取端口和第一VSS端子。 第一带状电池具有第一带电池VSS区域。 第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。 第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。
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公开(公告)号：US08767498B2
公开(公告)日：2014-07-01
申请号：US13285357
申请日：2011-10-31
IPC分类号： G11C17/14
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译： 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。
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公开(公告)号：US08704376B2
公开(公告)日：2014-04-22
申请号：US13443467
申请日：2012-04-10
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译： 布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。 井在底层。 第一多晶硅区位于第一掺杂区和第二掺杂区之间。 第二聚合区位于第三掺杂区和第四掺杂区之间。 第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。 第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。 阱被配置为用作晶体管的体积并从第二电源接收第二电压值。
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公开(公告)号：US08692580B2
公开(公告)日：2014-04-08
申请号：US13407548
申请日：2012-02-28
IPC分类号： H03K3/00
CPC分类号： G01R27/08 , G11C7/062 , G11C17/18 , G11C2207/063 , H03F3/45179 , H03F2200/555 , H03F2203/45394 , H03F2203/45674
摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
摘要翻译： 放大电路包括偏置电路，参考电路，第一电路和放大子电路。 偏置电路被配置为提供偏置电流。 参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。 第一电路被配置为基于第一电流和第一电阻提供第二差分输入。 放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。
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公开(公告)号：US20140061851A1
公开(公告)日：2014-03-06
申请号：US13599654
申请日：2012-08-30
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/522 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
摘要翻译： 本文公开的方法和结构的实施例提供了形成和编程金属通孔保险丝的机制。 金属通孔保险丝和编程晶体管形成一次性可编程（OTP）存储单元。 金属通路保险丝具有高电阻，并且可以用低编程电压进行编程，从而扩展编程窗口。
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公开(公告)号：US20140032871A1
公开(公告)日：2014-01-30
申请号：US13560461
申请日：2012-07-27
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译： 电路包括跟踪写入电路和写入电路。 基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。 写信号用于存储单元的写入操作。
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公开(公告)号：US20130264718A1
公开(公告)日：2013-10-10
申请号：US13443467
申请日：2012-04-10
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译： 布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。 井在底层。 第一多晶硅区位于第一掺杂区和第二掺杂区之间。 第二聚合区位于第三掺杂区和第四掺杂区之间。 第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。 第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。 阱被配置为用作晶体管的体积并从第二电源接收第二电压值。
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公开(公告)号：US20130148439A1
公开(公告)日：2013-06-13
申请号：US13759791
申请日：2013-02-05
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.
摘要翻译： 一种存储器电路，包括连接到位线的至少一个存储单元。 存储电路还包括用于向位线提供位线参考电压VBLref的装置。 位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化进行调整，VBLref / VDD比范围为约0.4至约0.53。
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公开(公告)号：US08391094B2
公开(公告)日：2013-03-05
申请号：US12692534
申请日：2010-01-22
IPC分类号： G11C5/04
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBLref to the bit line, wherein a VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD.
摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和位线耦合。 存储电路包括用于向位线提供位线参考电压VBLref的装置，其中位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化而调节。
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