公开(公告)号：US10218365B1

公开(公告)日：2019-02-26

申请号：US15968550

申请日：2018-05-01

Applicant: Micro Lambda Wireless, Inc.

Inventor： Shlomo Argoetti

IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099 ,  H04B7/185 ,  H03L7/00

Abstract: It was found that certain VCO devices used in microwave frequency synthesizers exhibit prolonged ringing oscillation during extreme voltage jumps above a critical limit, but that this effect could be significantly reduced by splitting the voltage adjustment over multiple steps. This finding was used to improve the switching speed of such devices (e.g. wideband VCO with a computer processor, base frequency generator VCO and a frequency divider). Here, before implementing a command to switch frequencies (by changing the base frequency oscillator and frequency divider settings), the processor first determines if this change will require an extreme voltage jump likely to cause such oscillations. If so, the processor implements this voltage jump as a multiple step process, resulting in a significant reduction in the maximum time required to switch frequencies.

公开(公告)号：US09843086B1

公开(公告)日：2017-12-12

申请号：US15445629

申请日：2017-02-28

Applicant: MICRO LAMBDA WIRELESS, INC.

Inventor： Oleksandr Chenakin

IPC: H03B5/30 ,  H01P7/00 ,  H03B5/10 ,  H03B5/18

CPC classification number: H03B5/1852 ,  H03B5/10 ,  H03B5/1847 ,  H03B5/1882 ,  H03B5/30

Abstract: An apparatus and method for building and operating of a YIG-based filter-attenuator module with closed-loop control. The module combines both signal filtering and amplitude control functions by utilizing an yttrium-iron-garnet (YIG) resonator. A technique for a closed-loop calibration and control also disclosed. This apparatus and method provides a cost effective harmonic rejection/amplitude control solution for microwave test-and-measurement instruments such as signal generators and spectrum analyzers.

公开(公告)号：US09819308B1

公开(公告)日：2017-11-14

申请号：US15420048

申请日：2017-01-30

Applicant: MICRO LAMBDA WIRELESS, INC.

Inventor： Oleksandr Chenakin

IPC: H03K3/03 ,  H03B5/18 ,  H01P1/218 ,  H01P1/20 ,  H01P7/00

CPC classification number: H03B5/1882 ,  H01P1/20 ,  H01P1/218 ,  H01P7/00 ,  H03B5/18 ,  H03B5/1894 ,  H03B2201/0241 ,  H03B2201/035

Abstract: A dual-resonator YIG oscillator with a main YIG resonator and a stabilizing YIG resonator both suspended in a common magnetic field. The main YIG resonator takes on the high-Q factor aspects of the oscillator, while the stabilizing YIG resonator helps stabilize the operation of the main YIG resonator, and also allows the main YIG resonator operate at higher magnetic field strengths, achieving higher frequency operation. The stabilizing YIG resonator also enables the oscillator's active device to operate in a more linear, lower phase noise, regime. As compared to conventional YIG oscillators, the disclosed dual resonator YIG oscillator provides significant performance improvements, such as higher frequency operation, lower power consumption, higher tuning speed, and lower phase noise.

公开(公告)号：US09793904B1

公开(公告)日：2017-10-17

申请号：US15469434

申请日：2017-03-24

Applicant: MICRO LAMBDA WIRELESS, INC.

Inventor： Oleksandr Chenakin

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  H03K5/1252

CPC classification number: H03L7/087 ,  H03K5/1252 ,  H03L7/099 ,  H03L7/18

Abstract: An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.

公开(公告)号：US09734099B1

公开(公告)日：2017-08-15

申请号：US15499640

申请日：2017-04-27

Applicant: Micro Lambda Wireless, Inc.

Inventor： Shlomo Argoetti

IPC: G06F3/00 ,  G06F13/16 ,  G06F13/10

CPC classification number: G06F13/1689 ,  G06F13/102 ,  G06F13/1673 ,  G06F13/4282

Abstract: System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.