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    SCHEMATIC-BASED LAYOUT MIGRATION
    1.
    发明申请
    SCHEMATIC-BASED LAYOUT MIGRATION 审中-公开
    基于模式的布局迁移

    公开(公告)号：US20120233576A1

    公开(公告)日：2012-09-13

    申请号：US13043761

    申请日：2011-03-09

    Applicant: Geoffrey R. Barrows ,  Derick G. Behrends ,  William J. Craig ,  Michael S. Gray ,  Matthew T. Guzowski ,  Kevin W. McCullen ,  Rani Narayan ,  Robert F. Walker

    Inventor： Geoffrey R. Barrows ,  Derick G. Behrends ,  William J. Craig ,  Michael S. Gray ,  Matthew T. Guzowski ,  Kevin W. McCullen ,  Rani Narayan ,  Robert F. Walker

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells.

    Abstract translation: 方法，系统，计算机等实施例将原始集成电路设计接收到计算机化设备中。 本文中的方法使用计算机化设备自动地用原始集成电路设计中的至少一些原始单元替换替换单元。 每个替换单元格具有与任何特定设计尺寸无关的初始单元格大小。 这里的方法将集成电路设计的原始设计尺寸自动地改变为改变的设计尺寸，并且将每个替换单元的初始单元尺寸自动地单独地改变为不同的尺寸。 基于每个替换单元的改变的设计尺寸中所需的不同的空间量，将至少两个不同的替换单元从初始单元大小改变为不同的尺寸减小量。

    Context aware sub-circuit layout modification
    2.
    发明授权
    Context aware sub-circuit layout modification 失效
    上下文感知子电路布局修改

    公开(公告)号：US07735042B2

    公开(公告)日：2010-06-08

    申请号：US11831998

    申请日：2007-08-01

    Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

    Abstract translation: 公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。 该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION
    4.
    发明申请
    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
    背景知识子电路布局修改

    公开(公告)号：US20090037851A1

    公开(公告)日：2009-02-05

    申请号：US11831998

    申请日：2007-08-01

    Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

    Abstract translation: 公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。 该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

    SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION
    5.
    发明申请
    SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION 有权
    用于在布局移动中固定引脚错配的系统和方法

    公开(公告)号：US20140019931A1

    公开(公告)日：2014-01-16

    申请号：US13546562

    申请日：2012-07-11

    Applicant: Kevin W. MCCULLEN ,  Matthew T. GUZOWSKI ,  Rani NARAYAN ,  Xiaoping TANG ,  Xin YUAN

    Inventor： Kevin W. MCCULLEN ,  Matthew T. GUZOWSKI ,  Rani NARAYAN ,  Xiaoping TANG ,  Xin YUAN

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.

    Abstract translation: 提供了用于在布局迁移中固定引脚不匹配的方法来交换库单元。 具体地，提供了一种方法，其包括在第一技术中从库单元收集关于第一技术引脚的信息。 该方法还包括在第二技术中用库单元交换第一技术中的库单元。 该方法还包括在第二技术中从库单元收集关于第二技术引脚的信息。 该方法还包括构建引脚映射表，其被配置为将第一技术引脚映射到第二技术引脚。 该方法还包括将布局从第一技术缩放到第二技术。 该方法还包括基于引脚映射表来修改布局，以在满足第二技术的基本规则的同时将至少一个第一技术引脚与至少一个第二技术引脚匹配。

    Layout optimization using parameterized cells
    9.
    发明授权
    Layout optimization using parameterized cells 有权
    使用参数化单元格进行布局优化

    公开(公告)号：US07865848B2

    公开(公告)日：2011-01-04

    申请号：US11846017

    申请日：2007-08-28

    Applicant: Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

    Inventor： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

    Abstract translation: 包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。 该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。 然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。 该方法可以基于与参数相关的约束来可选地调整物理设计形状。

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