公开(公告)号：US07446690B2

公开(公告)日：2008-11-04

申请号：US11556982

申请日：2006-11-06

申请人： Oliver C. Kao

发明人： Oliver C. Kao

IPC分类号： H03M1/12

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03M1/002 ,  H03M1/146 ,  H03M1/365

摘要： An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

摘要翻译： 公开了一种用于在可编程逻辑器件中提供模数转换器（ADC）的装置和方法。 多个多用途输入/输出（I / O）块被配置为提供模数转换和其他I / O功能。 多个多用途I / O块也配置为在禁止ADC模式时节省功耗。

公开(公告)号：US06768333B1

公开(公告)日：2004-07-27

申请号：US10437862

申请日：2003-05-13

申请人： Oliver C. Kao ,  Gladwyn O. D'Souza

发明人： Oliver C. Kao ,  Gladwyn O. D'Souza

IPC分类号： G01R3126

CPC分类号： G01R31/3016 ,  G01R31/31715

摘要： A test circuit aids in accurately measuring the input pin to output pin signal propagation speed through an integrated circuit by providing a D flip-flop in the signal path near the output pad to register the arrival of a test signal transition. The flip-flop is clocked at various clock frequencies. At the high frequencies, test signal transitions applied at the input pad coincident with a clock transition having not arrived at the output pad in time to be registered at the next clock transition. At lower clock frequencies, the test transition has time to propagate through the integrated circuit and thus will be registered by the flip-flop. By successively lowering the clock frequency and sending test signals through the circuit, one-half of that clock period that just registers the test signal transition corresponds to the input-to-output delay time being measured.

摘要翻译： 测试电路有助于通过在输出焊盘附近的信号路径中提供D触发器来准确测量输入引脚以输出引脚信号传播速度，以注册测试信号转换的到达。 触发器以各种时钟频率进行定时。 在高频时，在输入焊盘处施加的测试信号转换与未在时间上到达输出焊盘的时钟转换一致，以在下一个时钟转换时被注册。 在较低的时钟频率下，测试转换有时间传播通过集成电路，因此将由触发器进行寄存。 通过连续降低时钟频率并通过电路发送测试信号，刚刚注册测试信号转换的时钟周期的一半对应于被测量的输入到输出延迟时间。

公开(公告)号：US07197299B2

公开(公告)日：2007-03-27

申请号：US10752630

申请日：2004-01-07

申请人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Lawrence D. Engh ,  Peter Holzmann ,  Oliver C. Kao ,  Carl R. Palmer ,  Aditya Raina

发明人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Lawrence D. Engh ,  Peter Holzmann ,  Oliver C. Kao ,  Carl R. Palmer ,  Aditya Raina

IPC分类号： H04Q7/22 ,  H04B1/28

CPC分类号： H04M1/725 ,  G11C27/005 ,  H04M1/6041 ,  H04M1/6505

摘要： A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrated device that includes a plurality of signal paths, a microphone automatic gain control (“AGC”) circuit, volume control and filtering circuit, speaker driver circuit, gain selectable analog input, auxiliary input and output paths, configurable summation amplifiers having mixing features, multilevel analog memory storage array, and user selectable programming duration.

摘要翻译： 描述了多级模拟录音和播放系统。 模拟录音和回放系统提供了各种模拟处理功能，以增强系统级集成度。 模拟录音和回放系统是一个完全可配置的集成设备，包括多个信号路径，麦克风自动增益控制（“AGC”）电路，音量控制和滤波电路，扬声器驱动电路，增益可选模拟输入，辅助输入和 输出路径，具有混合特征的可配置求和放大器，多级模拟存储器存储阵列和用户可选择的编程持续时间。

公开(公告)号：US07437584B2

公开(公告)日：2008-10-14

申请号：US11362654

申请日：2006-02-27

申请人： Oliver C. Kao

发明人： Oliver C. Kao

IPC分类号： G06F1/32

CPC分类号： H03K19/1774 ,  H03K19/17728 ,  H03K19/17784

摘要： An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.

摘要翻译： 一种用于降低具有多个逻辑块和宏小区的可编程逻辑器件（PLD）中的功耗的装置和方法。 通过检测每个宏单元中的可编程开关值并基于开关值产生时钟控制信号来降低功耗。 时钟控制信号控制宏单元缓冲器，用于补偿输入到宏单元的时钟信号的失真。 如果宏单元没有使用时钟信号，宏单元缓冲器被禁止，从而防止不必要的切换和功耗。

公开(公告)号：US20080106452A1

公开(公告)日：2008-05-08

申请号：US11556982

申请日：2006-11-06

申请人： Oliver C. Kao

发明人： Oliver C. Kao

IPC分类号： H03M1/36 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03M1/002 ,  H03M1/146 ,  H03M1/365

摘要： An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

摘要翻译： 公开了一种用于在可编程逻辑器件中提供模数转换器（ADC）的装置和方法。 多个多用途输入/输出（I / O）块被配置为提供模数转换和其他I / O功能。 多个多用途I / O块也配置为在禁止ADC模式时节省功耗。

公开(公告)号：US07183801B2

公开(公告)日：2007-02-27

申请号：US10937817

申请日：2004-09-08

申请人： Oliver C. Kao ,  Nancy D. Kunnari

发明人： Oliver C. Kao ,  Nancy D. Kunnari

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to a first load path. The load path couples to a latch ring, which receives configuration data from the first memory. An array of configuration latches receives the configuration from the latch ring and effects a configuration of the programmable device. A write-back path couples the latch ring and first configuration memory. A write-back controller manages write-back operations of configuration data from the latch ring to the configuration memory. A second configuration controller is coupled to a second configuration memory, which is coupled to a second load path. The second controller and second memory operate like the first. The write-back controller can be configured to couple to the second memory and facilitate development processes by a writing-back developmental configurations.

摘要翻译： 第一配置控制器将配置数据加载到可编程逻辑器件中。 第一控制器与第一配置存储器耦合，并且管理存储器与第一负载路径的耦合。 负载路径耦合到锁存环，其从第一存储器接收配置数据。 一组配置锁存器从锁存环接收配置，并实现可编程器件的配置。 写回路径耦合锁存环和第一配置存储器。 写回控制器管理从锁存环到配置存储器的配置数据的回写操作。 第二配置控制器耦合到第二配置存储器，其被耦合到第二负载路径。 第二个控制器和第二个存储器像第一个操作一样运行。 回写控制器可以被配置为耦合到第二存储器并且通过回写开发配置来促进开发过程。

公开(公告)号：US06765433B1

公开(公告)日：2004-07-20

申请号：US10393583

申请日：2003-03-20

申请人： Oliver C. Kao

发明人： Oliver C. Kao

IPC分类号： G05F110

CPC分类号： G06F1/3203 ,  G05F1/56

摘要： Integrated circuit device that uses tristate switching means to disconnect input/output pins from input buffers during a power down mode, thereby preventing current leakage through partially turned on MOS transistors inside input buffers. A transition detection means connected between the input/output pins and the controlling inputs of the tristate switching means monitors electronic signal at the input/output pins while the chip is in a power-down mode and turns on the tristate switching means when a signal transition is detected.

摘要翻译： 使用三态切换装置的集成电路装置在掉电模式期间将输入/输出引脚与输入缓冲器断开，从而防止输入缓冲器内的部分导通的MOS晶体管的电流泄漏。 连接在输入/输出引脚和三态切换装置的控制输入之间的转换检测装置在芯片处于掉电模式时监视输入/输出引脚处的电子信号，并且当信号转换时接通三态切换装置 被检测到。