公开(公告)号：US20250157929A1

公开(公告)日：2025-05-15

申请号：US19022581

申请日：2025-01-15

Applicant: SOCIONEXT INC.

Inventor： Koshiro DATE

IPC: H01L23/528 ,  H10D30/67 ,  H10D62/10 ,  H10D84/85

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.

公开(公告)号：US20250151268A1

公开(公告)日：2025-05-08

申请号：US19013630

申请日：2025-01-08

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H10B20/00 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10

Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

公开(公告)号：US12284828B2

公开(公告)日：2025-04-22

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H10D84/90

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

公开(公告)号：US12273085B2

公开(公告)日：2025-04-08

申请号：US17837562

申请日：2022-06-10

Applicant: Socionext Inc.

Inventor： Vlad Cretu

IPC: H03H11/24

Abstract: Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

公开(公告)号：US20250063711A1

公开(公告)日：2025-02-20

申请号：US18939347

申请日：2024-11-06

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.

公开(公告)号：US20250029923A1

公开(公告)日：2025-01-23

申请号：US18772766

申请日：2024-07-15

Applicant: Socionext Inc.

Inventor： Masato NAKOSHI

IPC: H01L23/528 ,  H01L23/00

Abstract: A semiconductor device includes a first pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in the plan view; a second pad; a third wiring connected to the second pad in the first direction in the plan view; and a fourth wiring connected to the second pad in the second direction in the plan view. The second wiring is located between the third wiring and the first pad in the second direction, and the fourth wiring is located between the first wiring and the second pad in the second direction.

公开(公告)号：US20250006635A1

公开(公告)日：2025-01-02

申请号：US18886493

申请日：2024-09-16

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20250000487A1

公开(公告)日：2025-01-02

申请号：US18882246

申请日：2024-09-11

Applicant: Socionext Inc.

Inventor： Naoto ADACHI

IPC: A61B8/00

Abstract: An ultrasonic probe includes a transducer, a self-diagnosis circuit configured to perform inspection of the transducer, and an output part configured to output information that is in accordance with a result of the inspection performed by the self-diagnosis circuit.

公开(公告)号：US20240431088A1

公开(公告)日：2024-12-26

申请号：US18825831

申请日：2024-09-05

Applicant: Socionext Inc.

Inventor： Masanobu HIROSE

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

Abstract: A 2-port SRAM cell includes load transistors, drive transistors, access transistors, a read drive transistor, and a read access transistor. Buried interconnects corresponding to write-bit lines, respectively are formed in a buried interconnect layer so as to extend in a first direction. Interconnects corresponding to a read-word line and a write-word line, respectively are formed in an interconnect layer above the buried interconnect layer so as to extend in a second direction.

公开(公告)号：US20240420301A1

公开(公告)日：2024-12-19

申请号：US18823247

申请日：2024-09-03

Applicant: Socionext Inc.

Inventor： Nobutaka YAMAGISHI ,  Martin MAIER

IPC: G06T7/00 ,  G06T1/00 ,  G06T3/18

Abstract: A display control device includes an insertion unit configured to insert a determination image into a static region of time-series images, the static region being a region in which a pixel value does not change over time, a processing unit configured to execute warping processing on an image into which the determination image is inserted, and a determination unit configured to determine whether or not a result of a CRC computation performed on the static region of the image after the warping processing matches first reference information.