公开(公告)号：US20150279970A1

公开(公告)日：2015-10-01

申请号：US14231466

申请日：2014-03-31

Applicant: STMicroelctronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

Abstract translation: 通过直接从金属栅极传输，将SOI应用引入到SOI FinFET器件的沟道中。 特别是在SOI器件中，从金属栅极到沟道的应力传递效率接近100％。 可以通过选择在栅极堆叠中使用的不同材料作为体栅极材料，栅极衬垫或功函数材料，或者通过在栅极沉积期间改变处理参数来对鳍状物通道施加拉伸或压缩应力 工作功能材料。 因此，分别形成P-栅极和N-栅极。 适合用作应力源的栅极材料包括用于NFET的钨（W）和用于PFET的氮化钛（TiN）。 光学平面化材料有助于图案化应力诱导金属栅极。 公开了简化的工艺流程，其中形成隔离区而不需要单独的掩模层，并且不使用栅极侧壁间隔物。

公开(公告)号：US09162339B2

公开(公告)日：2015-10-20

申请号：US14035281

申请日：2013-09-24

Applicant: STMicroelctronics, Inc.

Inventor： John H. Zhang

IPC: B24B37/005 ,  B24B27/00 ,  B24B49/04

CPC classification number: B24B37/005 ,  B24B27/0076 ,  B24B49/04

Abstract: An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.

Abstract translation: 自适应均匀抛光系统配备有反馈控制，以在抛光操作期间应用局部调整。 所公开的自适应均匀抛光系统特别适用于半导体工业。 这种自适应均匀抛光系统包括保持半导体晶片的可旋转头部和被构造成与晶片的暴露表面接触的处理单元。 处理单元包括可旋转的宏观垫和多个可旋转的微垫，其可以以不同的转速和压力抛光暴露表面的不同部分。 因此，通过将定制的处理应用于不同的区域，可以增强暴露表面的均匀性。 定制处理可以包括使用不同的垫材料和几何形状。 自适应均匀抛光系统的参数是可编程的，基于在制造过程中的其他操作的原位数据或数据，使用先进的过程控制。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US08987780B2

公开(公告)日：2015-03-24

申请号：US13907752

申请日：2013-05-31

Applicant: STMicroelctronics, Inc.

Inventor： John H Zhang ,  Cindy Goldberg ,  Walter Kleemeier

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract translation: 公开了石墨烯封盖HEMT器件及其制造方法。 石墨烯封盖的HEMT器件包括一个或多个石墨烯帽，其增强用于高频，高能量应用（例如无线电信）中的示例性AlGaN / GaN异质结构晶体管的器件性能和/或可靠性。 所公开的HEMT装置利用石墨烯的非凡材料特性。 其中一个石墨烯帽作为晶体管下面的散热器，而另一个石墨烯帽稳定晶体管的源极，漏极和栅极区域，以防止在大功率操作期间的开裂。 公开了一种工艺流程，用于用原子厚的石墨烯层替代先前用于防止裂纹的三层膜堆，而不会使装置性能降低。 此外，所公开的HEMT器件包括六边形氮化硼粘附层，以便于将复合氮化物半导体沉积到石墨烯上。