公开(公告)号：US20080079508A1

公开(公告)日：2008-04-03

申请号：US11644506

申请日：2006-12-22

申请人： Sang-Jin Byun ,  Cheon-Soo Kim

发明人： Sang-Jin Byun ,  Cheon-Soo Kim

IPC分类号： H03B5/08

CPC分类号： H03B5/06 ,  H03B5/08 ,  H03B27/00

摘要： Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and −90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller. The LC quadrature VCO includes a first LC tank for generating a second clock signal and a fourth clock signal, a second LC tank for generating a first clock signal and a third clock signal, a phase detector for receiving the clock signals from the first LC tank and the second LC tank, and detecting whether a phase difference between the clocks is +90° or −90°, and a controller for discriminating whether phase information detected by the phase detector is equivalent to a phase difference between clocks required by the external signal processing unit, and changing an operation mode of the first LC tank and/or the second LC tank on the basis of the discrimination result of the phase difference between the clocks.

公开(公告)号：US20120106689A1

公开(公告)日：2012-05-03

申请号：US13347056

申请日：2012-01-10

申请人： Sang Jin Byun

发明人： Sang Jin Byun

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/085 ,  H03L7/0898 ,  H04L7/033

摘要： A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

摘要翻译： 公开了一种时钟和数据恢复电路。 根据本发明的实施例的时钟和数据恢复电路使用由包括线性相位检测器和二进制相位检测器构成的混合相位检测器。 由于时钟和数据恢复电路基本上由线性相位检测器，电荷泵，环路滤波器，压控振荡器和D触发器构成，以恢复时钟和数据，相位检测器增益与接收到的抖动无关 数据和恢复时钟，并且可以使用二进制相位检测器和电荷泵控制器对电荷泵的上/下电流的大小进行微调，从而补偿接收数据与恢复时钟之间的相位偏移 。

公开(公告)号：US20110158025A1

公开(公告)日：2011-06-30

申请号：US12648317

申请日：2009-12-29

申请人： Jin-Youp CHA ,  Sang-Jin BYUN

发明人： Jin-Youp CHA ,  Sang-Jin BYUN

IPC分类号： G11C17/16

CPC分类号： G11C29/785 ,  G11C17/16

摘要： A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.

摘要翻译： 半导体器件包括感测单元，其被配置为感测编程感测节点的值是否在预定范围内，连接到编程感测节点的熔丝，编程电压提供单元，其被配置为向编程感测节点提供编程电压， 以及传送单元，其被配置为响应于感测单元的感测结果传送编程感测节点的值。

公开(公告)号：US07751521B2

公开(公告)日：2010-07-06

申请号：US11280187

申请日：2005-11-15

申请人： Sang-Jin Byun ,  Hyun-Kyu Yu

发明人： Sang-Jin Byun ,  Hyun-Kyu Yu

IPC分类号： H03D3/24

CPC分类号： H03L7/107 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H04L7/033

摘要： A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed ¼ as fast as that of received data; a second loop having a phase detection unit operating at a speed ¼ as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

摘要翻译： 时钟和数据恢复装置降低了电流消耗并且使得易于集成。 本发明的装置包括第一回路，其包括频率/相位检测单元，第一电荷泵单元，复用单元，滤波单元和以与接收数据速度相同的速度运行的压控振荡器单元; 第二回路，其具有以接收数据速度快的速度操作的相位检测单元，适用于相位检测单元的第二电荷泵单元，多路复用单元，滤波单元和压控振荡器单元; 频率锁定检测单元，用于判断反馈时钟信号的频率是否在期望的频率范围内; 以及用于从接收到的数据恢复数据的数据恢复单元。

公开(公告)号：US20100090761A1

公开(公告)日：2010-04-15

申请号：US12511323

申请日：2009-07-29

申请人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H03D3/00

CPC分类号： H04L27/233 ,  H04L27/2338

摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.

摘要翻译： 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。

公开(公告)号：US07429874B2

公开(公告)日：2008-09-30

申请号：US11451962

申请日：2006-06-13

申请人： Sang Jin Byun ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Hyun Kyu Yu

IPC分类号： H03K19/094

CPC分类号： H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513

摘要： Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

摘要翻译： 提供了一种适用于多层堆叠CMOS电流模式逻辑（CML）的复制偏置电路，并且在使用低电源电压的应用领域中稳定地使用。 复制偏置电路对构成电子电路的目标晶体管的栅极施加参考电压。 复制偏置电路包括用于保持低于晶体管的阈值电压的电压差的副阈值电压发生器; 以及包括通过参考形成电流流路的构成装置的尺寸而设计的装置的复制路径，所述电流流路包括电子电路中的目标晶体管。 利用复制偏置电路，即使在低电源电压下，多层堆叠CMOS电流模式逻辑（CML）电路也能稳定地工作。

公开(公告)号：US20080079504A1

公开(公告)日：2008-04-03

申请号：US11778133

申请日：2007-07-16

申请人： Sang Jin BYUN ,  Cheon Soo KIM

发明人： Sang Jin BYUN ,  Cheon Soo KIM

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B27/00

摘要： Provided is a quadrature voltage controlled oscillator having only one resonant mode characteristic. The quadrature voltage controlled oscillator has a structure in which two clocks generated from respective LC resonant circuits are 90 degrees out of phase with each other using a phase detector and a loop filter, instead of a general structure in which two LC tank resonant circuits are mutually coupled to constitute an LC quadrature voltage controlled oscillator. The quadrature voltage controlled oscillator includes two resonant circuits having the same oscillation frequency; and a phase controller receiving oscillation clocks of the two resonant circuits to control at least one of oscillation phases of the two resonant circuits according to a phase difference between the two oscillation clocks.

摘要翻译： 提供了仅具有一个谐振模式特性的正交压控振荡器。 正交压控振荡器具有这样的结构，其中使用相位检测器和环路滤波器从相应的LC谐振电路产生的两个时钟彼此相差90度，而不是两个LC谐振电路谐振电路相互的一般结构 耦合以构成LC正交压控振荡器。 正交压控振荡器包括具有相同振荡频率的两个谐振电路; 以及相位控制器，接收两个谐振电路的振荡时钟，以根据两个振荡时钟之间的相位差来控制两个谐振电路的振荡相位中的至少一个。

公开(公告)号：US06952126B2

公开(公告)日：2005-10-04

申请号：US10438178

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0895

摘要： A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

摘要翻译： 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M 1和M 2，以及M 3和M 4）来消除输入信号的馈通，并且还消除了电荷泵中的上/下电流的失配 通过使用反馈应用新的副本偏移来实现宽电压输出范围。

公开(公告)号：US07079600B2

公开(公告)日：2006-07-18

申请号：US10438297

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03D3/00

CPC分类号： H04L27/1563

摘要： A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

摘要翻译： 公开了一种用于提供使用DLL的FSK解调器和解调方法的系统和方法，该解调方法检测与两个调制频率对应的方波的上升沿的时间顺序和中间频率，并将相关频率解调为数据。 FSK解调器包括带通滤波器，用于转换滤波成方波的频率的波形的限幅器，用于从幅度限制器接收方波并延迟方波延迟时间的延迟线，延迟 用于接收来自幅度限制器的输出信号和来自延迟线的输出信号的触发器（DFF），在给定时间确定两个输入信号的哪个上升沿较早，并将该确定结果作为数据输出， 以及锁定延迟线的延迟时间的DLL电路。

公开(公告)号：US08699649B2

公开(公告)日：2014-04-15

申请号：US13347056

申请日：2012-01-10

申请人： Sang Jin Byun

发明人： Sang Jin Byun

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/085 ,  H03L7/0898 ,  H04L7/033

摘要： A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

摘要翻译： 公开了一种时钟和数据恢复电路。 根据本发明的实施例的时钟和数据恢复电路使用由包括线性相位检测器和二进制相位检测器构成的混合相位检测器。 由于时钟和数据恢复电路基本上由线性相位检测器，电荷泵，环路滤波器，压控振荡器和D触发器构成，以恢复时钟和数据，相位检测器增益与接收到的抖动无关 数据和恢复时钟，并且可以使用二进制相位检测器和电荷泵控制器对电荷泵的上/下电流的大小进行微调，从而补偿接收数据与恢复时钟之间的相位偏移 。