公开(公告)号：US07079600B2

公开(公告)日：2006-07-18

申请号：US10438297

申请日：2003-05-13

Applicant: Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

Inventor： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC: H03D3/00

CPC classification number: H04L27/1563

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract translation: 公开了一种用于提供使用DLL的FSK解调器和解调方法的系统和方法，该解调方法检测与两个调制频率对应的方波的上升沿的时间顺序和中间频率，并将相关频率解调为数据。 FSK解调器包括带通滤波器，用于转换滤波成方波的频率的波形的限幅器，用于从幅度限制器接收方波并延迟方波延迟时间的延迟线，延迟 用于接收来自幅度限制器的输出信号和来自延迟线的输出信号的触发器（DFF），在给定时间确定两个输入信号的哪个上升沿较早，并将该确定结果作为数据输出， 以及锁定延迟线的延迟时间的DLL电路。

公开(公告)号：US07456063B2

公开(公告)日：2008-11-25

申请号：US11523212

申请日：2006-09-19

Applicant: Sang Jin Byun ,  Hyun Kyu Yu

Inventor： Sang Jin Byun ,  Hyun Kyu Yu

IPC: H01L21/8242

CPC classification number: H01L27/0207

Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

Abstract translation: 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。

公开(公告)号：US20120106689A1

公开(公告)日：2012-05-03

申请号：US13347056

申请日：2012-01-10

Applicant: Sang Jin Byun

Inventor： Sang Jin Byun

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/085 ,  H03L7/0898 ,  H04L7/033

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

Abstract translation: 公开了一种时钟和数据恢复电路。 根据本发明的实施例的时钟和数据恢复电路使用由包括线性相位检测器和二进制相位检测器构成的混合相位检测器。 由于时钟和数据恢复电路基本上由线性相位检测器，电荷泵，环路滤波器，压控振荡器和D触发器构成，以恢复时钟和数据，相位检测器增益与接收到的抖动无关 数据和恢复时钟，并且可以使用二进制相位检测器和电荷泵控制器对电荷泵的上/下电流的大小进行微调，从而补偿接收数据与恢复时钟之间的相位偏移 。

公开(公告)号：US20100090761A1

公开(公告)日：2010-04-15

申请号：US12511323

申请日：2009-07-29

Applicant: Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

Inventor： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC: H03D3/00

CPC classification number: H04L27/233 ,  H04L27/2338

Abstract: A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.

Abstract translation: 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。

公开(公告)号：US07429874B2

公开(公告)日：2008-09-30

申请号：US11451962

申请日：2006-06-13

Applicant: Sang Jin Byun ,  Hyun Kyu Yu

Inventor： Sang Jin Byun ,  Hyun Kyu Yu

IPC: H03K19/094

CPC classification number: H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513

Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Abstract translation: 提供了一种适用于多层堆叠CMOS电流模式逻辑（CML）的复制偏置电路，并且在使用低电源电压的应用领域中稳定地使用。 复制偏置电路对构成电子电路的目标晶体管的栅极施加参考电压。 复制偏置电路包括用于保持低于晶体管的阈值电压的电压差的副阈值电压发生器; 以及包括通过参考形成电流流路的构成装置的尺寸而设计的装置的复制路径，所述电流流路包括电子电路中的目标晶体管。 利用复制偏置电路，即使在低电源电压下，多层堆叠CMOS电流模式逻辑（CML）电路也能稳定地工作。

公开(公告)号：US06952126B2

公开(公告)日：2005-10-04

申请号：US10438178

申请日：2003-05-13

Applicant: Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

Inventor： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC: H03L7/089 ,  H03L7/06

CPC classification number: H03L7/0895

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract translation: 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M 1和M 2，以及M 3和M 4）来消除输入信号的馈通，并且还消除了电荷泵中的上/下电流的失配 通过使用反馈应用新的副本偏移来实现宽电压输出范围。

公开(公告)号：US08699649B2

公开(公告)日：2014-04-15

申请号：US13347056

申请日：2012-01-10

Applicant: Sang Jin Byun

Inventor： Sang Jin Byun

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/085 ,  H03L7/0898 ,  H04L7/033

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

Abstract translation: 公开了一种时钟和数据恢复电路。 根据本发明的实施例的时钟和数据恢复电路使用由包括线性相位检测器和二进制相位检测器构成的混合相位检测器。 由于时钟和数据恢复电路基本上由线性相位检测器，电荷泵，环路滤波器，压控振荡器和D触发器构成，以恢复时钟和数据，相位检测器增益与接收到的抖动无关 数据和恢复时钟，并且可以使用二进制相位检测器和电荷泵控制器对电荷泵的上/下电流的大小进行微调，从而补偿接收数据与恢复时钟之间的相位偏移 。

公开(公告)号：US07994851B2

公开(公告)日：2011-08-09

申请号：US12511323

申请日：2009-07-29

Applicant: Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

Inventor： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC: H04L27/06 ,  H03D3/18

CPC classification number: H04L27/233 ,  H04L27/2338

Abstract: A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.

Abstract translation: 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。

公开(公告)号：US20070134852A1

公开(公告)日：2007-06-14

申请号：US11523212

申请日：2006-09-19

Applicant: Sang Jin Byun ,  Hyun Kyu Yu

Inventor： Sang Jin Byun ,  Hyun Kyu Yu

IPC: H01L21/82

CPC classification number: H01L27/0207

Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

Abstract translation: 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。

公开(公告)号：US06844761B2

公开(公告)日：2005-01-18

申请号：US10437417

申请日：2003-05-12

Applicant: Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

Inventor： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC: H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract translation: 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。