PLL FREQUENCY SYNTHESIZER
    2.
    发明申请
    PLL FREQUENCY SYNTHESIZER 审中-公开
    PLL频率合成器

    公开(公告)号:US20100052747A1

    公开(公告)日:2010-03-04

    申请号:US12530171

    申请日:2008-02-08

    IPC分类号: H03L7/06

    摘要: A PLL frequency synthesizer 1 according to one embodiment of the present invention is provided with a frequency divider 30, a phase comparator 40, a charge pump 50, a loop filter 60, a voltage controlled oscillator 70, and a changeover switch (within the switching unit 80). The loop filter 60 has a reference potential on a semiconductor substrate as a ground potential, and the changeover switch is formed on the semiconductor substrate 2 and switches connection between an intermediate node of the loop filter 60 and the reference potential on the semiconductor substrate 2 to switch the time constant of the loop filter 60.

    摘要翻译: 根据本发明的一个实施例的PLL频率合成器1具有分频器30,相位比较器40,电荷泵50,环路滤波器60,压控振荡器70和转换开关(在开关 单位80)。 环路滤波器60在半导体衬底上具有作为接地电位的参考电位,并且转换开关形成在半导体衬底2上,并且将环路滤波器60的中间节点与半导体衬底2上的参考电位之间的连接切换到 切换环路滤波器60的时间常数。

    Method of manufacturing a SAW device
    3.
    发明授权
    Method of manufacturing a SAW device 有权
    制造SAW器件的方法

    公开(公告)号:US07467447B2

    公开(公告)日:2008-12-23

    申请号:US11088920

    申请日:2005-03-25

    IPC分类号: H04R17/10 C23C14/34

    摘要: In a SAW device comprising a piezoelectric single crystal substrate and electrodes on a surface thereof, the substrate is obtained by slicing a LiTaO3 or LiNbO3 material such that a plane containing axis X and perpendicular to a new axis Y obtained by rotating axis Y about axis X by an angle of 33°±9° becomes the substrate surface, and each electrode is a layered film including a titanium nitride layer and an aluminum layer thereon. The aluminum layer containing no grain boundaries ensures high efficiency, long life SAW devices experiencing no increase of electrical resistance.

    摘要翻译: 在包括压电单晶衬底和其表面上的电极的SAW器件中,通过将LiTaO 3或LiNbO 3材料切片使得包含轴线X并垂直于通过绕轴线X旋转的Y轴获得的新轴线Y的平面来获得衬底 33°±9°的角度成为基板表面,并且每个电极是其上包括氮化钛层和铝层的分层膜。 不含晶界的铝层确保高效率,长寿命的SAW器件不会增加电阻。

    SAW device and manufacturing method
    4.
    发明授权
    SAW device and manufacturing method 有权
    SAW器件及制造方法

    公开(公告)号:US06903488B2

    公开(公告)日:2005-06-07

    申请号:US10251811

    申请日:2002-09-23

    摘要: In a SAW device comprising a piezoelectric single crystal substrate and electrodes on a surface thereof, the substrate is obtained by slicing a LiTaO3 or LiNbO3 material such that a plane containing axis X and perpendicular to a new axis Y obtained by rotating axis Y about axis X by an angle of 33°±9° becomes the substrate surface, and each electrode is a layered film including a titanium nitride layer and an aluminum layer thereon. The aluminum layer containing no grain boundaries ensures high efficiency, long life SAW devices experiencing no increase of electrical resistance.

    摘要翻译: 在包括压电单晶衬底和其表面上的电极的SAW器件中,通过将LiT 3 O 3或LiNbO 3材料切片使得含有轴的平面 X并垂直于通过使轴线Y围绕轴线X旋转33°±9°的角度获得的新轴线Y成为基板表面,并且每个电极是其上包括氮化钛层和铝层的层状膜。 不含晶界的铝层确保高效率,长寿命的SAW器件不会增加电阻。

    PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME
    5.
    发明申请
    PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME 审中-公开
    相位比较电路和PLL合成器

    公开(公告)号:US20090201094A1

    公开(公告)日:2009-08-13

    申请号:US12160734

    申请日:2007-01-11

    申请人: Shigeki Ohtsuka

    发明人: Shigeki Ohtsuka

    IPC分类号: H03L7/08

    CPC分类号: H03D13/00 H03L7/10 H03L7/1976

    摘要: The phase comparison circuit according to an embodiment of the present invention comprises a fractional frequency divider 31 which generates a fractional frequency-divided signal Svn obtained by performing fractional frequency division on a clock on the basis of a control signal from a control circuit 32, a first integer frequency divider 33 which generates a first integer frequency-divided signal obtained by performing integer frequency division on the fractional frequency-divided signal Svn, a second integer frequency divider 34 which generates a second integer frequency-divided signal obtained by performing integer frequency division on a reference clock, a first selection circuit 35 which selectively outputs either the fractional frequency-divided signal Svn or the first integer frequency-divided signal on the basis of a switching signal, a second selection circuit 36 which selectively outputs either the reference clock or the second integer frequency-divided signal on the basis of the switching signal from the control circuit 32, and a phase comparator 37 which generates a comparison signal which represents the frequency difference and phase difference between the output signal from the first selection circuit 35 and the output signal from the second selection circuit 36.

    摘要翻译: 根据本发明实施例的相位比较电路包括一个分数分频器31,该分数分频器31产生通过基于来自控制电路32的控制信号对时钟进行分数分频而获得的分数分频信号Svn, 第一整数分频器33,其生成通过对分数分频信号Svn执行整数分频而获得的第一整数分频信号;第二整数分频器34,其生成通过执行整数分频获得的第二整数分频信号 在参考时钟上,第一选择电路35,其选择性地输出基于切换信号的分数分频信号Svn或第一整数分频信号;第二选择电路36,其选择性地输出参考时钟或 基于第二整数分频信号 来自控制电路32的切换信号和相位比较器37,其产生表示来自第一选择电路35的输出信号与来自第二选择电路36的输出信号之间的频率差和相位差的比较信号。

    Buffer circuit
    7.
    发明授权
    Buffer circuit 有权
    缓冲电路

    公开(公告)号:US06225839B1

    公开(公告)日:2001-05-01

    申请号:US09449219

    申请日:1999-11-24

    申请人: Shigeki Ohtsuka

    发明人: Shigeki Ohtsuka

    IPC分类号: H03K300

    CPC分类号: H03F1/56 H03K19/00376

    摘要: To provide a buffer circuit that is able to achieve a reduction of the input current and a high input impedance by compensating the base current of a transistor, and to avoid a lowering of the input dynamic range by means of a current compensation circuit. By means of transistor P2, the base voltage of transistor Q2 is established in response to the signal of input node ND1 of the differential circuit, and the emitter voltage of transistor Q2 is set at virtually the same level as the reference voltage Vref. The collector current IC2 of transistor P2 is the same as the base current of transistor Q2, and is established with the amplification ratio of transistor Q2 as well as the current I2 of current source IS2. The collector current IC1 of transistor P1 is made equal to IC2, and when the current amplification ratios of transistors Q1 and Q2 are made equal, the base current of transistor Q1 can be sufficiently compensated by means of the collector current IC1 of transistor P1, and the input current IIN of the buffer circuit will be reduced.

    摘要翻译: 提供一种能够通过补偿晶体管的基极电流来实现输入电流降低和高输入阻抗的缓冲电路,并且通过电流补偿电路来避免输入动态范围的降低。 通过晶体管P2,晶体管Q2的基极电压响应于差分电路的输入节点ND1的信号而建立,晶体管Q2的发射极电压被设定在与参考电压Vref几乎相同的电平。 晶体管P2的集电极电流IC2与晶体管Q2的基极电流相同,并且以晶体管Q2的放大率以及电流源IS2的电流I2建立。 使晶体管P1的集电极电流IC1等于IC2,当晶体管Q1和Q2的电流放大率相等时,可以通过晶体管P1的集电极电流IC1充分补偿晶体管Q1的基极电流, 缓冲电路的输入电流IIN将减小。

    Saw device and manufacturing method
    8.
    发明申请
    Saw device and manufacturing method 有权
    锯装置及制造方法

    公开(公告)号:US20050162039A1

    公开(公告)日:2005-07-28

    申请号:US11088920

    申请日:2005-03-25

    摘要: In a SAW device comprising a piezoelectric single crystal substrate and electrodes on a surface thereof, the substrate is obtained by slicing a LiTaO3 or LiNbO3 material such that a plane containing axis X and perpendicular to a new axis Y obtained by rotating axis Y about axis X by an angle of 33°±9° becomes the substrate surface, and each electrode is a layered film including a titanium nitride layer and an aluminum layer thereon. The aluminum layer containing no grain boundaries ensures high. efficiency, long life SAW devices experiencing no increase of electrical resistance.

    摘要翻译: 在包括压电单晶衬底和其表面上的电极的SAW器件中,通过将LiT 3 O 3或LiNbO 3材料切片使得含有轴的平面 X并垂直于通过使轴线Y围绕轴线X旋转33°±9°的角度获得的新轴线Y成为基板表面,并且每个电极是其上包括氮化钛层和铝层的层状膜。 不含晶界的铝层确保高。 效率高,寿命长的SAW器件不会增加电阻。