公开(公告)号：US07463626B2

公开(公告)日：2008-12-09

申请号：US10155517

申请日：2002-05-24

Applicant: Subhash C. Roy ,  David K. Toebes ,  Michael M. Renault ,  Steven E. Benoit ,  Igor Zhovnirovsky

Inventor： Subhash C. Roy ,  David K. Toebes ,  Michael M. Renault ,  Steven E. Benoit ,  Igor Zhovnirovsky

IPC: H04L12/56

CPC classification number: H04L12/6402 ,  H04J3/0682 ,  H04J3/0685 ,  H04J3/0688 ,  H04J2203/0025 ,  H04J2203/0026 ,  H04L7/10 ,  H04L2012/6413

Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Abstract translation: 公开了携带TDM和分组数据的分布式交换机中的相位和频率漂移和抖动补偿的方法和装置。 这些方法包括在开关的不同阶段插入可编程的填充时间，以允许缓冲区填充，以不同的时钟驱动服务处理器（线路卡），并将服务处理器（线路卡）同步到交换结构，提供冗余的交换矩阵时钟 以及用于自动地将一个冗余时钟替换为失败的时钟的方法，提供每个具有不同时钟的冗余交换结构和用于当一个交换结构失败时自动替换另一个交换结构的方法。 本发明的装置包括多个服务处理器（线路卡），开关元件和时钟发生器。 还公开了一种基于FPGA的示例性时钟发生器。

公开(公告)号：US06321331B1

公开(公告)日：2001-11-20

申请号：US09064474

申请日：1998-04-22

Applicant: Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

Inventor： Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

IPC: G06F930

CPC classification number: G06F11/3636 ,  G06F11/3656

Abstract: A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register. The event history buffer is loaded with more detailed information about the instruction last executed when the first decoder indicates that the last instruction was an exception or a jump to a register, and when there is a change in state of an interrupt line or an internal processor exception. An exemplary implementation of the debugging interface is embodied on an ASIC chip having three processors. Each processor is provided with a first and second decoders and a single event history buffer for all processors is provided on the chip.

Abstract translation: 调试接口包括耦合到处理器的定序器的一对解码器和事件历史缓冲器。 第一解码器耦合到定序器的程序计数器和处理器的指令RAM。 第二解码器耦合到定序器的原因寄存器，并且事件历史缓冲器也耦合到原因寄存器。 第一解码器提供三比特实时输出，其表示逐周期的处理器活动。 三位输出指示七种不同的条件：处理器执行的最后一条指令是否为inc，异常，没有事件历史缓冲区条目的异常，还是采取分支，是否从上一个时钟周期起都没有执行指令 ，以及跳转是否立即跳转或跳转到注册表。 当第一解码器指示最后一条指令是异常或跳转到寄存器时，以及当中断线或内部处理器的状态发生变化时，事件历史缓冲器被加载有关最后执行的指令的更详细信息 例外。 调试接口的示例性实现体现在具有三个处理器的ASIC芯片上。 每个处理器设置有第一和第二解码器，并且在芯片上提供用于所有处理器的单个事件历史缓冲器。

公开(公告)号：US06636515B1

公开(公告)日：2003-10-21

申请号：US09717999

申请日：2000-11-21

Applicant: Subhash C. Roy ,  Santanu Das ,  Daniel C. Upp ,  William B. Lipp ,  Jitender K. Vij ,  Michael M. Renault ,  Frederick R. Carter ,  Rajen S. Ramchandani

Inventor： Subhash C. Roy ,  Santanu Das ,  Daniel C. Upp ,  William B. Lipp ,  Jitender K. Vij ,  Michael M. Renault ,  Frederick R. Carter ,  Rajen S. Ramchandani

IPC: H04L1228

CPC classification number: H04L12/6402 ,  H04L2012/6413

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。 在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此，该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

公开(公告)号：US6134653A

公开(公告)日：2000-10-17

申请号：US64446

申请日：1998-04-22

Applicant: Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

Inventor： Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/462

Abstract: A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles. In addition, one set of general purpose registers can be loaded by a coprocessor while another set of general purpose registers is in use by the ALU. According to a presently preferred embodiment, each of the three sets of general purpose registers includes twenty-eight thirty-two bit registers. In addition, according to the presently preferred embodiment, a single set of four thirty-two bit registers is provided for use in any context. The set of common registers is used to store information which is used by more than one context.

Abstract translation: RISC处理器包括定序器，寄存器ALU（RALU），数据RAM和协处理器接口。 定序器包括一个Nx32位指令RAM，它通过协处理器接口从外部存储器引导。 RALU包括用于存储三个上下文的四端口寄存器文件和一个ALU。 根据本发明的ISA（指令集架构）支持多达八个协处理器。 本发明的一个重要特征是提供多组通用寄存器用于存储若干上下文。 根据目前的优选实施例，提供三组通用寄存器作为RALU的一部分，并且提供新的操作码用于在通用寄存器组之间切换。 使用多组通用寄存器，可以在三个处理周期内完成上下文切换。 此外，一组通用寄存器可由协处理器加载，另一组通用寄存器由ALU使用。 根据目前优选的实施例，三组通用寄存器中的每一个包括二十八位32位寄存器。 另外，根据目前的优选实施例，提供了一组四个32位寄存器，用于任何上下文。 该公共寄存器集用于存储由多个上下文使用的信息。

公开(公告)号：US5893162A

公开(公告)日：1999-04-06

申请号：US796085

申请日：1997-02-05

Applicant: Joseph C. Lau ,  Subhash C. Roy ,  Dirk L. M. Callaerts ,  Ivo Edmond Nicole Vandeweerd

Inventor： Joseph C. Lau ,  Subhash C. Roy ,  Dirk L. M. Callaerts ,  Ivo Edmond Nicole Vandeweerd

IPC: G06F5/06 ,  G06F12/02 ,  H04L12/56 ,  H04Q11/04 ,  G06F12/00

CPC classification number: H04Q11/0478 ,  G06F12/023 ,  G06F5/065 ,  G06F2205/064 ,  H04L2012/5681

Abstract: Apparatus and methods for allocating shared memory utilizing linked lists are provided which are particularly useful in telecommunications applications such as ATM. A management RAM contained within a VLSI circuit is provided for controlling the flow of data into and out of a shared memory (data RAM), and stores information regarding a number of link lists and a free link list in the shared memory, and a block pointer to unused RAM locations. A head pointer, tail pointer, block counter and empty flag are stored for each data link list. The head and tail pointers each include a block pointer and a position counter. The block counter contains the number of blocks used in the particular queue. The empty flag indicates whether the queue is empty. The free link list includes a head pointer, a block counter, and an empty flag. Each memory page of the shared data RAM receiving the incoming data includes locations for storing data. The last location of the last page in a block of shared data RAM memory is preferably used to store a next-block pointer plus parity information. If there are no more blocks in the queue, that last location is set to all ones. An independent agent is utilized in the background to monitor the integrity of the link list structure. Using the methods and apparatus of the invention, four operations are defined for ATM cell management: cell write, cell read, queue clear, and link list monitoring.

Abstract translation: 提供了利用链表分配共享存储器的装置和方法，其在诸如ATM的电信应用中特别有用。 包含在VLSI电路内的管理RAM被提供用于控制进出共享存储器（数据RAM）的数据流，并将关于多个链接列表和空闲链接列表的信息存储在共享存储器中，以及块 指向未使用的RAM位置。 为每个数据链接列表存储头指针，尾指针，块计数器和空标志。 头和尾指针各包括一个块指针和一个位置计数器。 块计数器包含特定队列中使用的块数。 空标志表示队列是否为空。 免费链接列表包括头指针，块计数器和空标志。 接收输入数据的共享数据RAM的每个存储器页面包括用于存储数据的位置。 共享数据RAM存储器块中的最后一页的最后位置优选地用于存储下一个块指针加上奇偶校验信息。 如果队列中没有更多块，则将最后一个位置设置为全部。 在后台使用独立代理来监视链接列表结构的完整性。 使用本发明的方法和装置，为ATM信元管理定义了四个操作：信元写入，信元读取，清除清单和链路列表监视。

公开(公告)号：US07061935B1

公开(公告)日：2006-06-13

申请号：US09717147

申请日：2000-11-21

Applicant: Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani

Inventor： Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani

IPC: H04J3/16 ,  H04J3/22

CPC classification number: H04L41/0896 ,  H04J3/16 ,  H04Q2213/1329 ,  H04Q2213/13292 ,  H04Q2213/13367

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。 在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此，该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

公开(公告)号：US06636511B1

公开(公告)日：2003-10-21

申请号：US09717472

申请日：2000-11-21

Applicant: Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani ,  Daniel C. Upp

Inventor： Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani ,  Daniel C. Upp

IPC: H04L1228

CPC classification number: H04L12/6402 ,  H04L2012/6413

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。 在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此，该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

公开(公告)号：US06356561B1

公开(公告)日：2002-03-12

申请号：US09561034

申请日：2000-04-28

Applicant: Joseph C. Lau ,  Subhash C. Roy ,  John F. Gilsdorf

Inventor： Joseph C. Lau ,  Subhash C. Roy ,  John F. Gilsdorf

IPC: H04J316

CPC classification number: H04Q11/0478 ,  H04L2012/5652

Abstract: A method for the fair and efficient transfer of variable length packets using fixed length “segments” utilizes a modified UTOPIA interface with three additional signals added, i.e. start of packet (SOP), end of packet (EOP), and most significant byte (MSB). Packets are broken into “segments” of fixed, but programmable, length. The start of a segment is marked by a pulse on the UTOPIA start of cell (SOC) signal line. The start of a packet is marked by a pulse on the SOP signal line. The end of a packet is marked by a pulse on the EOP signal line. According to a presently preferred embodiment, bytes are transferred via a 16-bit bus. When a packet ends with a single byte on the bus, the MSB signal line is asserted to distinguish it from a packet which ends with two bytes on the bus. The invention can be expanded to accommodate buses wider than 16-bits by making the EOP a multiple bit signal. The extra signals added to the standard UTOPIA interface by the invention are not involved in segment transfer. Segments are transferred in the same manner that ATM cells are transferred using standard UTOPIA technology. Rather, the extra signals are used by a PHY device to reconstruct packets which were transferred over the interface. Accordingly, a single interface according to the invention can be used to transfer both variable length packets and ATM cells.

Abstract translation: 使用固定长度“段”公平有效地传输可变长度分组的方法利用经修改的UTOPIA接口，其中添加了三个附加信号，即分组开始（SOP），分组结束（EOP）和最高有效字节（MSB ）。 分组被分解成固定的，但可编程的长度的“段”。 段的开始由UTOPIA启动单元（SOC）信号线上的脉冲标记。 分组的开始由SOP信号线上的脉冲标记。 分组的结尾用EOP信号线上的脉冲标记。 根据目前的优选实施例，通过16位总线传送字节。 当分组以总线上的单个字节结束时，MSB信号线被断言以将其与总线上以两个字节结束的分组区分开。 通过使EOP成为多位信号，可以扩展本发明以适应比16位宽的总线。 通过本发明添加到标准UTOPIA接口的额外信号不涉及段传送。 分段以与使用标准UTOPIA技术传输ATM信元相同的方式传送。 相反，PHY设备使用额外的信号来重建通过接口传送的分组。 因此，根据本发明的单个接口可以用于传送可变长度分组和ATM信元。

公开(公告)号：US06205155B1

公开(公告)日：2001-03-20

申请号：US09263288

申请日：1999-03-05

Applicant: Eugene L. Parrella ,  Subhash C. Roy

Inventor： Eugene L. Parrella ,  Subhash C. Roy

IPC: H04J302

CPC classification number: H04L12/5601 ,  H04L49/107 ,  H04L49/255 ,  H04L49/506

Abstract: An ATM switch system has a plurality of input ports and output ports all having associated buffers, and a source traffic control system which includes a shared bus coupling the ports, and a switch controller or arbiter which controls the transfer of data among the ports via the shared bus. ATM cells placed on the shared bus include an internal destination address which designates the output port within the switch to which the ATM cell is destined. The switch controller monitors the internal destination addresses of the ATM cells, and increments a counter associated with the destination port when the destination corresponds, and decrements other counters which do not correspond to the destination. Accordingly, bursts for a particular output port causes the count of the associated counter to grow large; whereas frequent or long breaks cause the count to drop. The counts are compared to a high threshold which alerts the arbiter that the buffer of the output port being tracked is in danger of overflowing. Upon receiving the alert, the arbiter either stalls the bus by refusing to grant access to the bus until the counter decrements below the first threshold, or grants bus access to the input port associated with the output port on the theory that the input port will not be sending data to its own output. A low threshold is utilized to declare that a burst is over and to free the counter for tracking a new burst to the same or a different output port.

Abstract translation: ATM交换机系统具有多个具有相关联的缓冲器的输入端口和输出端口，以及包括耦合端口的共享总线的源业务控制系统，以及通过该端口控制端口之间的数据传输的交换机控制器或仲裁器 共享公共汽车。 放置在共享总线上的ATM信元包括内部目的地地址，该内部目的地地址指定ATM信元去往的交换机内的输出端口。 交换机控制器监视ATM信元的内部目的地址，并且在目的地对应时增加与目的地端口相关联的计数器，并且递减与目的地不对应的其他计数器。 因此，针对特定输出端口的突发导致相关联计数器的计数增大; 而频繁或长时间的休息导致计数下降。 将计数与高阈值进行比较，警报仲裁器正在跟踪输出端口的缓冲区有溢出的危险。 在接收到警报后，仲裁器将通过拒绝授予对总线的访问来停止总线，直到计数器递减到低于第一阈值，或者根据输入端口不会对输出端口关联的输入端口授予总线访问 将数据发送到自己的输出。 利用低阈值来声明突发已经结束，并释放计数器以跟踪新的脉冲串到相同或不同的输出端口。

公开(公告)号：US5774465A

公开(公告)日：1998-06-30

申请号：US650910

申请日：1996-05-17

Applicant: Joseph C. Lau ,  Subhash C. Roy

Inventor： Joseph C. Lau ,  Subhash C. Roy

IPC: H04L12/56 ,  H04Q11/04

CPC classification number: H04L49/3009 ,  H04L49/201 ,  H04L49/203 ,  H04L49/3081 ,  H04L49/30

Abstract: An ATM destination switch includes an ATM layer device coupled to a physical layer device. The ATM layer device includes a ATM layer interface which receives incoming ATM cells, a processor which is typically with an associated translation RAM, and an ATM layer to physical layer interface. The processor decodes the incoming ATM cell to obtain a VPI/VCI, and provides additional routing information (session number) for the cell for multicast purposes. The cell with the additional routing information is forwarded to the physical layer device which has a header processor, a multicast indicator storage table, preferably in the form of a bit map, for storing output line indications by session number, and a plurality of ATM line output interfaces. The header processor receives the cell with the additional routing information, reads the additional routing information, accesses the multicast indicator storage table based on the additional routing information to determine to which output lines the cell is to be provided, and controls the copying of the cell for each output line so that it may be received at multiple destinations. Thus, an incoming cell which is to be multicast to multiple users connected to the physical layer side of the switch will be multicast to the multiple users using the single VPI/VCI chosen for the local multicast.

Abstract translation: ATM目的地交换机包括耦合到物理层设备的ATM层设备。 ATM层设备包括接收进入的ATM信元的ATM层接口，通常具有相关联的转换RAM的处理器，以及ATM层到物理层接口。 处理器对输入的ATM信元进行解码以获得VPI / VCI，为组播目的提供小区的附加路由信息（会话号）。 具有附加路由信息的小区被转发到物理层设备，该物理层设备具有头处理器，多播指示符存储表，优选地以位图的形式，用于通过会话号存储输出线指示，以及多个ATM线 输出接口。 标题处理器接收具有附加路由信息的小区，读取附加路由信息，基于附加路由信息访问多播指示符存储表，以确定要向其提供小区的哪条输出线，并控制小区的复制 对于每个输出线，使得其可以在多个目的地被接收。 因此，要使用连接到交换机的物理层侧的多个用户进行组播的传入单元将使用为本地组播选择的单个VPI / VCI向多个用户进行多播。