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1.发明申请DIGITAL WIDEBAND CLOSED LOOP PHASE MODULATOR WITH MODULATION GAIN CALIBRATION 有权数字宽带闭环相位调制器，具有调制增益校准公开(公告)号：US20130223564A1
公开(公告)日：2013-08-29
申请号：US13405583
申请日：2012-02-27
IPC分类号： H04L27/20
CPC分类号： H04L25/03343 , H04L27/2003 , H04L27/2032 , H04L27/368
摘要： One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.
摘要翻译： 本发明的一个实施例涉及一种具有锁相环和自适应控制的调制系统。 相位锁定环被配置为接收输入信号和自适应信号。 输入信号是未调制信号，例如相位分量或相位信号。 锁相环也被配置为提供误差信号和输出信号。 误差信号表示一个或多个调制误差。 输出信号是使用自适应信号校正的输入信号的调制版本，以减轻一个或多个调制误差。
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公开(公告)号：US20110084769A1
公开(公告)日：2011-04-14
申请号：US12578105
申请日：2009-10-13
CPC分类号： H03L7/099 , H03B2200/0092 , H03L7/093 , H03L7/1976 , H03L2207/05
摘要： A device comprises an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit comprises a frequency control input and is configured to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input. The processor circuit is configured to calculate, on the basis of the first input signal value, the second input signal value, the third input signal value, the first frequency value, the second frequency value, and the third frequency value, a second order coefficient of a polynomial oscillator characteristic relating values of the frequency of the oscillator signal to values of the input signal.
摘要翻译： 一种装置包括振荡器电路，控制电路，频率检测器电路和处理器电路。 振荡器电路包括频率控制输入，并且被配置为输出振荡器信号。 振荡器信号的频率取决于施加到频率控制输入的输入信号。 控制电路被配置为向频率控制输入施加第一输入信号值，第二输入信号值和第三输入信号值。 频率检测器电路被配置为当第一输入信号值被施加到频率控制输入时检测振荡器信号的第一频率值，当第二输入信号值被施加到频率控制时，振荡器信号的第二频率值 输入和第三频率值，当第三输入信号值被施加到频率控制输入时。 处理器电路被配置为基于第一输入信号值来计算第二输入信号值，第三输入信号值，第一频率值，第二频率值和第三频率值，二阶系数 多项式振荡器特性将振荡器信号的频率值与输入信号的值相关联。
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3.发明授权Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal 有权相位/频率检测器，锁相环，相位/频率检测方法以及产生振荡器信号的方法公开(公告)号：US07592874B2
公开(公告)日：2009-09-22
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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4.发明授权公开(公告)号：US07573348B2
公开(公告)日：2009-08-11
申请号：US11840408
申请日：2007-08-17
申请人： Thomas Bauernfeind , Linus Maurer
发明人： Thomas Bauernfeind , Linus Maurer
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/095 , H03L7/093 , H03L7/095 , H03L7/0991 , H03L7/187 , H03L7/1976
摘要： An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.
摘要翻译： 用于确定数字控制振荡器的梯度因子的装置具有数据对准装置和识别装置。 可以向数据对准装置提供调制信号，相位误差信号和振荡器控制字。 数据对准装置被配置为基于调制信号输出调制设置字，基于相位误差信号和参考间隔输出时间间隔幅度，并且基于振荡器控制字输出振荡器调制字。 识别装置被配置为基于调制设置字，时间间隔幅度和振荡器调制字来适应和输出梯度因子。
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5.发明申请Phase Locked Loop, Transceiver Device and Method for Generating an Oscillator Signal 有权锁相环，收发器装置和产生振荡器信号的方法公开(公告)号：US20080106341A1
公开(公告)日：2008-05-08
申请号：US11925379
申请日：2007-10-26
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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6.发明授权Digital wideband closed loop phase modulator with modulation gain calibration 有权带调制增益校准的数字宽带闭环相位调制器公开(公告)号：US09225562B2
公开(公告)日：2015-12-29
申请号：US13405583
申请日：2012-02-27
CPC分类号： H04L25/03343 , H04L27/2003 , H04L27/2032 , H04L27/368
摘要： One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.
摘要翻译： 本发明的一个实施例涉及一种具有锁相环和自适应控制的调制系统。 相位锁定环被配置为接收输入信号和自适应信号。 输入信号是未调制信号，例如相位分量或相位信号。 锁相环也被配置为提供误差信号和输出信号。 误差信号表示一个或多个调制误差。 输出信号是使用自适应信号校正的输入信号的调制版本，以减轻一个或多个调制误差。
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7.发明授权Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization 有权用于通过相位同步在第一时钟域和第二时钟域之间同步数据切换的装置公开(公告)号：US08826062B2
公开(公告)日：2014-09-02
申请号：US13113340
申请日：2011-05-23
申请人： Thomas Bauernfeind
发明人： Thomas Bauernfeind
CPC分类号： H04L7/0012 , G06F1/10 , H04L7/0029
摘要： An apparatus for synchronizing a data handover is disclosed. The calculator is clocked with a clock of a first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator and to adjust the synchronization pulse cycle duration information based on the phase information.
摘要翻译： 公开了一种同步数据切换的装置。 计算器用第一时钟域的时钟计时，并且被配置为提供描述在第二时钟域的时钟处的同步脉冲的时间位置的同步脉冲周期持续时间信息。 同步脉冲发生器用第二时钟域的时钟计时，并被配置为产生同步脉冲，使得同步脉冲位于由同步脉冲周期持续时间信息描述的时间位置。 相位信息提供器用第二时钟域的时钟计时，并且被配置为提供描述同步脉冲和第一时钟域的时钟之间的相位关系的相位信息。 反馈路径被配置为将相位信息反馈到计算器并且基于相位信息来调整同步脉冲周期持续时间信息。
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公开(公告)号：US08098104B2
公开(公告)日：2012-01-17
申请号：US12578105
申请日：2009-10-13
CPC分类号： H03L7/099 , H03B2200/0092 , H03L7/093 , H03L7/1976 , H03L2207/05
摘要： A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.
摘要翻译： 设备可以包括振荡器电路，控制电路，频率检测器电路和处理器电路。 振荡器电路可以包括用于输出振荡器信号的频率控制输入。 振荡器信号的频率取决于施加到频率控制输入的输入信号。 控制电路被配置为向频率控制输入施加第一输入信号值，第二输入信号值和第三输入信号值。 频率检测器电路被配置为当第一输入信号值被施加到频率控制输入时检测振荡器信号的第一频率值，当第二输入信号值被施加到频率控制时，振荡器信号的第二频率值 输入和第三频率值，当第三输入信号值被施加到频率控制输入时。
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9.发明申请APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN 有权用于同步第一时钟域和第二时钟域之间的数据切换的装置公开(公告)号：US20120303996A1
公开(公告)日：2012-11-29
申请号：US13113340
申请日：2011-05-23
申请人： Thomas Bauernfeind
发明人： Thomas Bauernfeind
IPC分类号： G06F1/12
CPC分类号： H04L7/0012 , G06F1/10 , H04L7/0029
摘要： Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase information provider and a feedback path. The calculator is clocked with a clock of the first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator. In addition, the calculator is configured to adjust the synchronization pulse cycle duration information based on the phase information.
摘要翻译： 本发明的实施例提供了一种用于在第一时钟域和第二时钟域之间同步数据切换的装置。 该装置包括计算器，同步脉冲发生器，相位信息提供器和反馈路径。 计算器用第一时钟域的时钟计时，并且被配置为提供描述在第二时钟域的时钟处的同步脉冲的时间位置的同步脉冲周期持续时间信息。 同步脉冲发生器用第二时钟域的时钟计时，并被配置为产生同步脉冲，使得同步脉冲位于由同步脉冲周期持续时间信息描述的时间位置。 相位信息提供器用第二时钟域的时钟计时，并且被配置为提供描述同步脉冲和第一时钟域的时钟之间的相位关系的相位信息。 反馈路径被配置为将相位信息反馈到计算器。 此外，计算器被配置为基于相位信息来调整同步脉冲周期持续时间信息。
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10.发明申请APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN 有权用于同步第一时钟域和第二时钟域之间的数据切换的装置公开(公告)号：US20120303994A1
公开(公告)日：2012-11-29
申请号：US13113730
申请日：2011-05-23
CPC分类号： H04L7/005 , G06F5/12 , G06F2205/061 , G06F2205/102 , H04L7/0012
摘要： Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is clocked with the clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage is configured to take over an input data value in synchronization with the first clock domain and to provide an output data value in synchronization with the second clock domain and in response to a current synchronization pulse. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the subsequent synchronization pulse such that the subsequent synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The fill level information provider is configured to provide a fill level information describing a fill level of the first-in-first-out storage. The feedback path is configured for feeding back the fill level information to the calculator that is further configured to adjust the synchronization pulse cycle duration information based on the fill level information.
摘要翻译： 本发明的实施例提供了一种用于在第一时钟域和第二时钟域之间同步数据切换的装置。 该装置包括计算器，先进先出存储器，同步脉冲发生器，填充级信息提供器和反馈路径。 计算器用第一时钟域的时钟计时，并且被配置为提供描述在第二时钟域的时钟处的同步脉冲的时间位置的同步脉冲周期持续时间信息。 先入先出存储被配置为与第一时钟域同步地接收输入数据值，并且响应于当前同步脉冲提供与第二时钟域同步的输出数据值。 同步脉冲发生器用第二时钟域的时钟计时，并被配置为产生后续的同步脉冲，使得随后的同步脉冲位于由同步脉冲周期持续时间信息描述的时间位置。 填充级别信息提供者被配置为提供描述先进先出存储器的填充级别的填充级别信息。 反馈路径被配置为将填充水平信息反馈到计算器，该计算器还被配置为基于填充水平信息来调整同步脉冲周期持续时间信息。
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