公开(公告)号：US20140125419A1

公开(公告)日：2014-05-08

申请号：US14155356

申请日：2014-01-15

申请人： Jun Zhang ,  Xiuqiang Xu

发明人： Jun Zhang ,  Xiuqiang Xu

IPC分类号： G01R31/28

CPC分类号： G01R31/282 ,  G01R31/2824

摘要： An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.

摘要翻译： 振荡电路产生电压信号。 通过内部测试电路测量电压信号的大小并与预定的上下电压信号进行比较。 如果电压信号的大小在预定的上下电压信号之间，则产生通过测试状态信号。 如果电压信号的幅度不在预定的上限和下限电压信号之间，则产生故障测试状态信号。

公开(公告)号：US20130285729A1

公开(公告)日：2013-10-31

申请号：US13607734

申请日：2012-09-09

申请人： Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

发明人： Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

IPC分类号： H03L5/00

CPC分类号： H03K3/0231 ,  H03B2201/0266 ,  H03K4/502 ,  H03K17/6871 ,  H03K2017/066 ,  H03K2217/0036 ,  H03K2217/0054

摘要： A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

摘要翻译： 半导体微调电路包括与并联耦合NMOS器件并联耦合的并联耦合PMOS器件和附加的一对虚设NMOS器件。 虚设NMOS器件与NMOS器件并联耦合。 用于内部时钟源的微调电路可以形成有用于选择微调电路的一个或多个微调电容器的这种开关阵列。 这种阵列具有低泄漏电流并且允许良好的微调线性度。

公开(公告)号：US20140139267A1

公开(公告)日：2014-05-22

申请号：US13716194

申请日：2012-12-16

申请人： Yang Wang ,  Jianzhou Wu ,  Xiuqiang Xu ,  Yizhong Zhang

发明人： Yang Wang ,  Jianzhou Wu ,  Xiuqiang Xu ,  Yizhong Zhang

IPC分类号： H03K3/00

CPC分类号： H03F3/45183 ,  H03F2200/513

摘要： A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage VB than the threshold value so that the overall transconductance of the buffer input stage remains constant.

摘要翻译： 轨到轨差分缓冲器输入级包括以电压跟随器配置连接到电源轨的n型和p型输入差分晶体管对。 参考电压发生器包括相对于共模输入电压产生动态参考电压的参考差分晶体管对。 虚拟的n型和p型晶体管对具有与输入差分对并联连接的电流传导路径，并且由动态参考电压控制，以在共模时将供电轨电流转移离开并停用相关输入差分对中的一个 输入电压比动态参考电压进一步远离阈值。 当共模输入电压比阈值更接近于动态参考电压VB时，这两个虚拟对导通并且两个输入差分对被激活，使得缓冲器输入级的整个跨导保持恒定。

公开(公告)号：US20120293270A1

公开(公告)日：2012-11-22

申请号：US13462823

申请日：2012-05-03

申请人： Jun ZHANG ,  Xiuqiang Xu

发明人： Jun ZHANG ,  Xiuqiang Xu

IPC分类号： G01R19/04

CPC分类号： G01R31/282 ,  G01R31/2824

摘要： An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.

摘要翻译： 振荡电路产生电压信号。 通过内部测试电路测量电压信号的大小并与预定的上下电压信号进行比较。 如果电压信号的大小在预定的上下电压信号之间，则产生通过测试状态信号。 如果电压信号的幅度不在预定的上限和下限电压信号之间，则产生故障测试状态信号。

公开(公告)号：US09726724B2

公开(公告)日：2017-08-08

申请号：US14554056

申请日：2014-11-26

申请人： Xiuqiang Xu ,  Yin Guo ,  Shayan Zhang ,  Wanggen Zhang ,  Xu Zhang ,  Yizhong Zhang

发明人： Xiuqiang Xu ,  Yin Guo ,  Shayan Zhang ,  Wanggen Zhang ,  Xu Zhang ,  Yizhong Zhang

IPC分类号： G01R31/26 ,  G01R31/3187 ,  G01R31/28

CPC分类号： G01R31/3187 ,  G01R31/2886

摘要： An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

公开(公告)号：US20150323590A1

公开(公告)日：2015-11-12

申请号：US14554056

申请日：2014-11-26

申请人： Xiuqiang Xu ,  Yin Guo ,  Shayan Zhang ,  Wanggen Zhang ,  Xu Zhang ,  Yizhong Zhang

发明人： Xiuqiang Xu ,  Yin Guo ,  Shayan Zhang ,  Wanggen Zhang ,  Xu Zhang ,  Yizhong Zhang

IPC分类号： G01R31/28

CPC分类号： G01R31/3187 ,  G01R31/2886

摘要： An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

摘要翻译： 包括处理器的集成电路还具有间接测量处理器中的静态电流的片上电流测试电路。 集成电路的电源电压引脚从外部测试单元接收电源电压，以向处理器供电。 当处理器与电源电压隔离并且时钟信号停止时，片上测试电路在预定的测试周期T期间测量跨处理器的电压变化。 电压变化提供对应于处理器的静态电流的指示。

公开(公告)号：US08773174B2

公开(公告)日：2014-07-08

申请号：US13716194

申请日：2012-12-16

申请人： Yang Wang ,  Jianzhou Wu ,  Xiuqiang Xu ,  Yizhong Zhang

发明人： Yang Wang ,  Jianzhou Wu ,  Xiuqiang Xu ,  Yizhong Zhang

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03F3/45183 ,  H03F2200/513

摘要： A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage VB than the threshold value so that the overall transconductance of the buffer input stage remains constant.

摘要翻译： 轨到轨差分缓冲器输入级包括以电压跟随器配置连接到电源轨的n型和p型输入差分晶体管对。 参考电压发生器包括相对于共模输入电压产生动态参考电压的参考差分晶体管对。 虚拟的n型和p型晶体管对具有与输入差分对并联连接的电流传导路径，并且由动态参考电压控制，以在共模时将供电轨电流转移离开并停用相关输入差分对中的一个 输入电压比动态参考电压进一步远离阈值。 当共模输入电压比阈值更接近于动态参考电压VB时，这两个虚拟对导通并且两个输入差分对被激活，使得缓冲器输入级的整个跨导保持恒定。

公开(公告)号：US08723612B2

公开(公告)日：2014-05-13

申请号：US13607734

申请日：2012-09-09

申请人： Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

发明人： Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

IPC分类号： H03K3/0231 ,  H03K4/502

CPC分类号： H03K3/0231 ,  H03B2201/0266 ,  H03K4/502 ,  H03K17/6871 ,  H03K2017/066 ,  H03K2217/0036 ,  H03K2217/0054

摘要： A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

摘要翻译： 半导体微调电路包括与并联耦合NMOS器件并联耦合的并联耦合PMOS器件和附加的一对虚设NMOS器件。 虚设NMOS器件与NMOS器件并联耦合。 用于内部时钟源的微调电路可以形成有用于选择微调电路的一个或多个微调电容器的这种开关阵列。 这种阵列具有低泄漏电流并且允许良好的微调线性度。

公开(公告)号：US08686798B2

公开(公告)日：2014-04-01

申请号：US13462823

申请日：2012-05-03

申请人： Jun Zhang ,  Xiuqiang Xu

发明人： Jun Zhang ,  Xiuqiang Xu

IPC分类号： H03L5/00 ,  G01R19/04

CPC分类号： G01R31/282 ,  G01R31/2824

摘要： An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.

摘要翻译： 振荡电路产生电压信号。 通过内部测试电路测量电压信号的大小并与预定的上下电压信号进行比较。 如果电压信号的大小在预定的上下电压信号之间，则产生通过测试状态信号。 如果电压信号的幅度不在预定的上限和下限电压信号之间，则产生故障测试状态信号。