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    System and method for controlling logical value and integrity of data in memory systems
    2.
    发明授权
    System and method for controlling logical value and integrity of data in memory systems 失效
    用于控制存储器系统中数据的逻辑值和完整性的系统和方法

    公开(公告)号：US06970382B2

    公开(公告)日：2005-11-29

    申请号：US11024560

    申请日：2004-12-29

    Applicant: Zeynep Toros ,  Esin Terzioglu ,  Ahmad O. Siksek ,  Gil I. Winograd ,  Ali Anvar

    Inventor： Zeynep Toros ,  Esin Terzioglu ,  Ahmad O. Siksek ,  Gil I. Winograd ,  Ali Anvar

    IPC: G11C16/12 ,  G11C16/34

    CPC classification number: G11C16/12

    Abstract: In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a bit line is coupled to the cell. A voltage generator is arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal. A controller generates a control signal, stores a predetermined one of logical values in a cell by generating a series of operating voltages, transmits the series of operating voltages, and determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line. The controller includes a charge integrity estimating module and determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.

    Abstract translation: 在数字存储器系统中，提供了控制由电荷表示的数据的逻辑值和完整性的系统和方法。 在一个实施例中，位线耦合到单元。 电压发生器被布置成产生响应于电压控制信号而变化的多个电池工作电压。 控制器产生控制信号，通过产生一系列工作电压将一个逻辑值存储在单元中，发送一系列工作电压，并且确定逻辑值中的预定的一个是否已被存储在单元中 到位线上的电压。 控制器包括电荷完整性估计模块，并且通过启动电荷完整性估计模块的操作来确定逻辑值中的预定的一个是否已经存储在该单元中。

    Non-volatile memory control techniques
    3.
    发明申请
    Non-volatile memory control techniques 失效
    非易失性存储器控制技术

    公开(公告)号：US20050111277A1

    公开(公告)日：2005-05-26

    申请号：US11024560

    申请日：2004-12-29

    Applicant: Zeynep Toros ,  Esin Terzioglu ,  Ahmad Siksek ,  Gil Winograd ,  Ali Anvar

    Inventor： Zeynep Toros ,  Esin Terzioglu ,  Ahmad Siksek ,  Gil Winograd ,  Ali Anvar

    IPC: G11C16/12 ,  G11C7/02

    CPC classification number: G11C16/12

    Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.

    Abstract translation: 数字存储器系统（30）包括存储单元（10），位线（12），电压发生器（320）和控制器（90）。 控制器被布置为通过产生从第一电压开始的一系列操作电压并且继续连续地更大的第一电压的工作电压来在电池中存储预定的逻辑值。 电压从电压发生器传输到电池。 在每个传送一系列工作电压之一之后，控制器使存储在单元中的电荷的至少一部分流入位线。 控制器响应于电荷流动来确定逻辑值中的预定的一个是否已经存储在该单元中。 在已经存储了预定的一个逻辑状态的情况下或者在连续较大的一连串操作电压中的一个等于第二电压的情况下，控制器终止该单元的一系列工作电压的传送。

    Imaging apparatus providing black level compensation of a successive approximation A/D converter
    6.
    发明授权
    Imaging apparatus providing black level compensation of a successive approximation A/D converter 有权
    成像装置提供逐次逼近A / D转换器的黑电平补偿

    公开(公告)号：US07317480B1

    公开(公告)日：2008-01-08

    申请号：US10000660

    申请日：2001-10-30

    Applicant: Kwang-Bo Cho ,  Michael Kaplinsky ,  Sandor L. Barna ,  Zeynep Toros ,  Igor Subbotin

    Inventor： Kwang-Bo Cho ,  Michael Kaplinsky ,  Sandor L. Barna ,  Zeynep Toros ,  Igor Subbotin

    IPC: H04N5/217 ,  H04N9/64 ,  H03M1/12

    CPC classification number: H03M1/1019 ,  H03M1/1215 ,  H03M1/46 ,  H04N5/361 ,  H04N5/374 ,  H04N9/045

    Abstract: Image sensor with a successive approximation A/D converter that automatically compensates for black level and provides a signal indicative of the difference between the reset level and the signal level. Black level for each of a plurality of color pixels may be obtained. This may be obtained from, for example, an image sensor with intentionally darkened pixels. Levels from these pixels are sampled, and an average of these pixels is used to form a black level for similarly-colored pixels. That black level is stored, and used to drive a D/A converter. Another D/A converter forms the actual conversion, and is compared to a reference. The reference is selected such that the output signal is automatically compensated for black level, and also corresponds to the difference between signal and reset.

    Abstract translation: 具有逐次逼近A / D转换器的图像传感器，其自动补偿黑电平并提供指示复位电平和信号电平之间的差异的信号。 可以获得多个彩色像素中的每一个的黑色电平。 这可以从例如具有有意变暗的像素的图像传感器获得。 对这些像素的电平进行采样，并且使用这些像素的平均来形成用于类似彩色像素的黑色电平。 存储黑色电平，并用于驱动D / A转换器。 另一个D / A转换器形成实际转换，并与参考进行比较。 选择参考，使得输出信号自动补偿黑电平，并且也对应于信号和复位之间的差异。

    Reduced leakage memory cell
    9.
    发明授权
    Reduced leakage memory cell 有权
    减少泄漏记忆体

    公开(公告)号：US06574136B1

    公开(公告)日：2003-06-03

    申请号：US09989595

    申请日：2001-11-20

    Applicant: Cyrus Afghahi ,  Sami Issa ,  Zeynep Toros

    Inventor： Cyrus Afghahi ,  Sami Issa ,  Zeynep Toros

    IPC: G11C11401

    CPC classification number: H01L27/10805 ,  G11C11/404 ,  H01L27/108

    Abstract: A random access memory cell (10) includes a first conductor line (12) and a second conductor line (14). A native device (16) is arranged to store charge. A high voltage threshold transistor (30) couples the native device to the first and second conductors.

    Abstract translation: 随机存取存储单元（10）包括第一导线（12）和第二导线（14）。 设置本地设备（16）以存储费用。 高电压阈值晶体管（30）将天然器件耦合到第一和第二导体。

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