利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.015 秒)

    Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof
    1.
    发明授权
    Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof 有权
    兼容的垂直双扩散金属氧化物半导体晶体管和横向双扩散金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US08530961B2

    公开(公告)日：2013-09-10

    申请号：US13384002

    申请日：2010-10-26

    申请人： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

    发明人： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

    IPC分类号： H01L29/66 ,  H01L21/336

    CPC分类号： H01L29/66712 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/8249 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7835

    摘要： A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.

    摘要翻译： 制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

    Radio frequency devices with enhanced ground structure.
    3.
    发明申请
    Radio frequency devices with enhanced ground structure. 有权
    射频设备具有增强的地面结构。

    公开(公告)号：US20090134953A1

    公开(公告)日：2009-05-28

    申请号：US12300464

    申请日：2007-05-17

    申请人： Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

    发明人： Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

    IPC分类号： H03H7/01

    CPC分类号： H01P1/184 ,  H01P1/203

    摘要： Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions.

    摘要翻译： 通过在衬底上沉积薄膜层并通过各种光刻技术对薄膜层进行图案化来形成可调谐射频（RF）器件，例如移相器和滤波器。 图案化薄膜金属层以形成多个电容器和电感器，留下紧邻电容器和电感器的至少两个接地区域。 由于接地区域的图案部分彼此电隔离。 通过电气桥接差分电位接地区来改善器件的性能。

    Method and system for dose control during an ion implantation process
    4.
    发明授权
    Method and system for dose control during an ion implantation process 失效
    离子注入过程中剂量控制的方法和系统

    公开(公告)号：US06797967B1

    公开(公告)日：2004-09-28

    申请号：US10082567

    申请日：2002-02-25

    申请人： Tom Tse ,  Zhiyong Zhao ,  David M. Hendrix

    发明人： Tom Tse ,  Zhiyong Zhao ,  David M. Hendrix

    IPC分类号： G21K500

    CPC分类号： H01J37/3171 ,  H01J2237/31703

    摘要： A method is presented for compensating for the effects of charge neutralization in calculating the ‘true’ ion dose, i.e., the dose assuming no changes of charge state of ions during an implantation process. An ion beam is generated under normal operating conditions, e.g., stable vacuum exists, and no target is being implanted. At least one additional detector would be positioned in the target chamber, and a dose measurement conducted simultaneously with a measurement of the beam current with the Faraday, which is located outside of the charge neutralization region, to establish a reference ratio. A wafer is then placed at the target location, and simultaneous measurements made with the additional detector and Faraday, as before, to determine the ratio between the beam current and the detector during wafer implantation. Any drift from the reference ratio indicates the dose error due to charge neutralization from wafer outgassing during implantation. Software for controlling various parameters could be configured to use the ratio drift data to change the dose counter to compensate for the dose error due to charge neutralization.

    摘要翻译： 提出了一种用于补偿电荷中和在计算“真实”离子剂量时的影响的方法，即假定在注入过程中离子的电荷状态没有变化的剂量。 在正常操作条件下产生离子束，例如存在稳定的真空，并且不会植入靶。 至少一个额外的检测器将被定位在目标腔室中，并且与位于电荷中和区域外侧的法拉第的射束电流的测量同时进行剂量测量，以建立参考比。 然后将晶片放置在目标位置，并且如前所述使用附加检测器和法拉第进行的同时测量来确定在晶片植入期间束电流和检测器之间的比率。 参考比值的任何偏差表示由植入过程中的晶片放气引起的电荷中和引起的剂量误差。 用于控制各种参数的软件可以配置为使用比率漂移数据来改变剂量计数器，以补偿由于电荷中和引起的剂量误差。

    Faraday system for ion implanters
    5.
    发明授权
    Faraday system for ion implanters 失效
    法拉第系统用于离子注入机

    公开(公告)号：US06723998B2

    公开(公告)日：2004-04-20

    申请号：US09950940

    申请日：2001-09-12

    申请人： Jack Bisson ,  Zhiyong Zhao ,  George Gammel ,  Daniel Alvarado ,  Craig Walker

    发明人： Jack Bisson ,  Zhiyong Zhao ,  George Gammel ,  Daniel Alvarado ,  Craig Walker

    IPC分类号： G01K100

    CPC分类号： H01J37/244 ,  H01J2237/24405 ,  H01J2237/31703

    摘要： A Faraday system for measuring ion beam current in an ion implanter or other ion beam treatment system includes a Faraday cup body defining a chamber which has an entrance aperture for receiving an ion beam, a suppression electrode positioned in proximity to the entrance aperture to produce electric fields for inhibiting escape of electrons from the chamber, and a magnet assembly positioned to produce magnetic fields for inhibiting escape of electrons from the chamber. The chamber may have a relatively small ratio of chamber depth to entrance aperture width.

    摘要翻译： 用于测量离子注入机或其他离子束处理系统中的离子束电流的法拉第系统包括法拉第杯体，其限定具有用于接收离子束的入口孔的腔室，位于入口孔附近的抑制电极，以产生电 用于抑制电子从腔室逃逸的场;以及磁体组件，其被定位成产生用于抑制电子从腔室逸出的磁场。 室可以具有相对小的室深度与入口孔宽度的比率。

    Radio frequency devices with enhanced ground structure
    6.
    发明授权
    Radio frequency devices with enhanced ground structure 有权
    射频设备具有增强的地面结构

    公开(公告)号：US08988169B2

    公开(公告)日：2015-03-24

    申请号：US12300464

    申请日：2007-05-17

    申请人： Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

    发明人： Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

    IPC分类号： H03H7/00 ,  H01P1/18 ,  H01P1/203

    CPC分类号： H01P1/184 ,  H01P1/203

    摘要： Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions.

    摘要翻译： 通过在衬底上沉积薄膜层并通过各种光刻技术对薄膜层进行图案化来形成可调谐射频（RF）器件，例如移相器和滤波器。 图案化薄膜金属层以形成多个电容器和电感器，留下紧邻电容器和电感器的至少两个接地区域。 由于接地区域的图案部分彼此电隔离。 通过电气桥接差分电位接地区来改善器件的性能。

    Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same
    7.
    发明授权
    Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same 有权
    确定器件晶片上掺杂区域的特性的方法以及用于实现其的系统

    公开(公告)号：US07504838B1

    公开(公告)日：2009-03-17

    申请号：US11381239

    申请日：2006-05-02

    申请人： Zhiyong Zhao ,  Christian Krueger

    发明人： Zhiyong Zhao ,  Christian Krueger

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2831 ,  H01L21/26513

    摘要： Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate. In another illustrative embodiment, the method includes providing an SOI substrate comprised of an active layer, the active layer having a thickness, illuminating an area of the substrate using a light source having a wavelength that is sufficiently long such that an excited region created in the active layer due to the illumination does not extend beyond the thickness of the active layer, and measuring an induced surface photovoltage resulting from the illumination.

    摘要翻译： 本文公开了确定器件晶片上的掺杂区域的特性的各种方法以及用于实现其的系统。 在一个说明性实施例中，该方法包括提供包括多个掩蔽区域，多个未掩模区域和形成在该衬底中的至少一个掺杂区域的器件衬底，确定该未屏蔽区域与该器件的掩蔽区域之间的比率 衬底，照射包括掩蔽区域，未掩蔽区域和至少一个掺杂区域的器件衬底的区域，以及测量器件衬底的感应表面光电压，同时考虑未掩蔽区域和掩蔽区域的掩蔽面积的比率 器件衬底。 在另一说明性实施例中，该方法包括提供由有源层构成的SOI衬底，有源层具有厚度，使用具有足够长的波长的光源照射衬底的区域，使得在 由于照明而导致的有源层不会超出有源层的厚度，并且测量由照明产生的感应表面光电压。

    Electronic and optical devices and methods of forming these devices
    10.
    发明申请
    Electronic and optical devices and methods of forming these devices 有权
    电子和光学装置以及形成这些装置的方法

    公开(公告)号：US20060228064A1

    公开(公告)日：2006-10-12

    申请号：US11444542

    申请日：2006-06-02

    申请人： Andrew Hunt ,  Robert Schwerzel ,  Yongdong Jiang ,  Zhiyong Zhao ,  Todd Polley

    发明人： Andrew Hunt ,  Robert Schwerzel ,  Yongdong Jiang ,  Zhiyong Zhao ,  Todd Polley

    IPC分类号： G02F1/035

    CPC分类号： G02F1/0316 ,  G02F1/0508 ,  H01G7/06 ,  H01L21/86 ,  H01L27/016 ,  H01L27/13 ,  H01L29/93

    摘要： Electronic and optical (or photonic) devices with variable or switchable properties and methods used to form these devices, are disclosed. More specifically, the present invention involves forming layers of conductive material and dielectric material or materials with varying conductivity and indexes of refraction to form various electronic and optical devices. One such layer of adjustable material is formed by depositing epitaxial or reduced grain boundary barium strontium titanate on the C-plane of sapphire.

    摘要翻译： 公开了具有可变或可切换特性的电子和光学（或光子）器件和用于形成这些器件的方法。 更具体地，本发明涉及形成具有导电性和折射率的导电材料和介电材料或材料的层，以形成各种电子和光学器件。 通过在蓝宝石的C平面上沉积外延或还原的晶界钡钛酸锶而形成一个这样的可调节材料层。