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公开(公告)号：US20250004828A1
公开(公告)日：2025-01-02
申请号：US18216314
申请日：2023-06-29
Applicant: ADVANCED MICRO DEVICES, INC. , XILINX, INC.
Inventor： Mark Unruh Wyse , Anthony Thomas Gutierrez , Paul Blinzer , Samuel Richard Bayliss
Abstract: A processor employs a hardware signal monitor to manage signaling for accelerators. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.
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公开(公告)号：US20240211134A1
公开(公告)日：2024-06-27
申请号：US18087964
申请日：2022-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Karthik Ramu Sangaiah , Anthony Thomas Gutierrez
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673
Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.
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公开(公告)号：US20230409336A1
公开(公告)日：2023-12-21
申请号：US17843640
申请日：2022-06-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Sriseshan Srikanth , Karthik Ramu Sangaiah , Anthony Thomas Gutierrez , Vedula Venkata Srikant Bharadwaj , John Kalamatianos
CPC classification number: G06F9/3853 , G06F9/3885 , G06F9/321
Abstract: In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine. A first count of data communications issued by the plurality of processing elements and a second count of data communications served by the plurality of processing elements are maintained. At least one additional instruction is determined for dispatch to the plurality of processing elements of the VLIW machine based on the first count and the second count. For example, an instruction that is independent of the instruction is determined for dispatch while the first count and the second count are unequal, and an instruction that is dependent on the instruction is determined for dispatch based on the first count and the second count being equal.
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公开(公告)号：US20230185575A1
公开(公告)日：2023-06-15
申请号：US17550878
申请日：2021-12-14
Applicant: Advanced Micro Devices, Inc.
CPC classification number: G06F9/3853 , G06F9/3885 , G06F9/30145 , G06F1/189
Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.
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公开(公告)号：US20250110792A1
公开(公告)日：2025-04-03
申请号：US18374263
申请日：2023-09-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen Alexander Zekany , Anthony Thomas Gutierrez
IPC: G06F9/50
Abstract: In accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. The host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. Further, the host processor submits the formatted task graph to a scalable input/output virtualization (SIOV) device, which directs the SIOV device to process the tasks of the task graph based on the order.
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Patent Agency Ranking
公开(公告)号：US20250004955A1
公开(公告)日：2025-01-02
申请号：US18215519
申请日：2023-06-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Anthony Thomas Gutierrez , Todd David Basso , Gabriel Hsiuwei Loh
IPC: G06F13/16 , G06F13/366
Abstract: Programmable I/O die devices and methods are described. An example system includes an input/output die (IOD) that couples a plurality of devices. The system also includes a programmable fabric included in the IOD. The programmable fabric implements interconnects for connecting the plurality of devices according to a reconfigurable topology defined by a configuration of the programmable fabric.
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公开(公告)号：US20250004806A1
公开(公告)日：2025-01-02
申请号：US18216310
申请日：2023-06-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Unruh Wyse , Anthony Thomas Gutierrez , Stephen Alexander Zekany , Paul Blinzer
IPC: G06F9/455
Abstract: A processing unit (e.g., a CPU) executes multiple processes, such as multiple virtual machines, wherein each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. A hardware signal manager (HSM) assigns each virtual signal to a physical signal of the system and assigns each virtual signal monitor to a physical signal monitor. Based on a process' interactions (e.g., signal operations) with a virtual signal monitor, the HSM executes corresponding interactions at the assigned physical signal monitor. The HSM thus virtualizes the physical signal monitors for the executing processes.
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公开(公告)号：US20240385872A1
公开(公告)日：2024-11-21
申请号：US18198981
申请日：2023-05-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Martha Massee Barker , Anthony Thomas Gutierrez , Mark Unruh Wyse , Ali Arda Eker
IPC: G06F9/48
Abstract: In accordance with the described techniques for aggregation and scheduling of accelerator executable tasks, an accelerator device includes a processing element array and a command processor to receive a plurality of fibers each including multiple tasks and dependencies between the multiple tasks. The command processor places a first fiber in a sleep pool based on a first task within the first fiber having an unresolved dependency, and the command processor further places a second fiber in a ready pool based on a second task within the second fiber having a resolved dependency. Based on the second fiber being in the ready pool, the command processor launches the second task to be executed by the processing element array.
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公开(公告)号：US12033238B2
公开(公告)日：2024-07-09
申请号：US17030852
申请日：2020-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Brian D. Emberling , Joseph Lee Greathouse , Anthony Thomas Gutierrez
Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.
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公开(公告)号：US20250005705A1
公开(公告)日：2025-01-02
申请号：US18764603
申请日：2024-07-05
Applicant: Advanced Micro Devices, Inc.
Inventor： Brian D. Emberling , Joseph Lee Greathouse , Anthony Thomas Gutierrez
Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.
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