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公开(公告)号：US20140298068A1
公开(公告)日：2014-10-02
申请号：US13854434
申请日：2013-04-01
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Stephen V. Kosonocky , Christopher Spence Oliver , Sudha Thiruvengadam , Carson D. Henrion
CPC classification number: G06F1/3287 , Y02D10/171
Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
Abstract translation: 集成电路装置包括布置在第一功率域内的第一模块，设置在作为第一功率域的子域的第二功率域中的第二模块，第一功率门控逻辑和第二功率门控逻辑。 第一电源门控逻辑为第一模块生成第一虚拟电源。 第二电源门控逻辑由第一虚拟电源供电，用于为第二电源域产生第二虚拟电源。
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公开(公告)号：US09405357B2
公开(公告)日：2016-08-02
申请号：US13854434
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen V. Kosonocky , Christopher Spence Oliver , Sudha Thiruvengadam , Carson D. Henrion
CPC classification number: G06F1/3287 , Y02D10/171
Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
Abstract translation: 集成电路装置包括布置在第一功率域内的第一模块，设置在作为第一功率域的子域的第二功率域中的第二模块，第一功率门控逻辑和第二功率选通逻辑。 第一电源门控逻辑为第一模块生成第一虚拟电源。 第二电源门控逻辑由第一虚拟电源供电，用于为第二电源域产生第二虚拟电源。
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公开(公告)号：US20190196839A1
公开(公告)日：2019-06-27
申请号：US15853169
申请日：2017-12-22
Applicant: Advanced Micro Devices, Inc.
CPC classification number: G06F9/3855 , G06F9/3005
Abstract: A system and method for increasing address generation operations per cycle is described. In particular, a unified address generation scheduler queue (AGSQ) is a single queue structure which is accessed by first and second pickers in a picking cycle. Picking collisions are avoided by assigning a first set of entries to the first picker and a second set of entries to the second picker. The unified AGSQ uses a shifting, collapsing queue structure to shift other micro-operations into issued entries, which in turn collapses the queue and re-balances the unified AGSQ. A second level and delayed picker picks a third micro-operation that is ready for issue in the picking cycle. The third micro-operation is picked from the remaining entries across the first set of entries and the second set of entries. The third micro-operation issues in a next picking cycle.
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