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公开(公告)号:US20230154555A1
公开(公告)日:2023-05-18
申请号:US18154372
申请日:2023-01-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: STEVEN RAASCH , GREG SADOWSKI , DAVID A. ROBERTS
CPC classification number: G11C16/3495 , G06F12/0246 , G06F3/0679 , G06F3/0616 , G11C16/3418 , G06F12/0223 , G06F9/50 , G11C16/349 , G11C29/70 , G06F3/064 , G11C11/4076 , G11C7/04 , G06F2212/1036 , G06F2212/7211
Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.
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公开(公告)号:US20240413035A1
公开(公告)日:2024-12-12
申请号:US18809578
申请日:2024-08-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: DAVID A. ROBERTS , GREG SADOWSKI , STEVEN RAASCH
IPC: H01L23/34 , G05B15/02 , G06F1/20 , H01L25/065
Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号:US20230143622A1
公开(公告)日:2023-05-11
申请号:US18152022
申请日:2023-01-09
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: DAVID A. ROBERTS , GREG SADOWSKI , STEVEN RAASCH
IPC: H01L23/34 , G05B15/02 , H01L25/065 , G06F1/20
CPC classification number: H01L23/34 , G05B15/02 , H01L25/0657 , G06F1/20 , H01L2225/06589
Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号:US20230325320A1
公开(公告)日:2023-10-12
申请号:US18185058
申请日:2023-03-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: DAVID A. ROBERTS
IPC: G06F12/0862 , G06F12/0815 , G06F12/0846
CPC classification number: G06F12/0848 , G06F12/0815 , G06F12/0862 , G06F2212/282 , G06F2212/602 , G06F2212/621
Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.
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公开(公告)号:US20220138103A1
公开(公告)日:2022-05-05
申请号:US17575461
申请日:2022-01-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: DAVID A. ROBERTS
IPC: G06F12/0846 , G06F12/0815 , G06F12/0862
Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.
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