METHOD AND APPARATUS FOR PROVIDING THERMAL WEAR LEVELING

    公开(公告)号:US20240413035A1

    公开(公告)日:2024-12-12

    申请号:US18809578

    申请日:2024-08-20

    Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

    METHOD AND APPARATUS FOR PROVIDING THERMAL WEAR LEVELING

    公开(公告)号:US20230143622A1

    公开(公告)日:2023-05-11

    申请号:US18152022

    申请日:2023-01-09

    Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

    METHOD AND APPARATUS FOR CONTROLLING CACHE LINE STORAGE IN CACHE MEMORY

    公开(公告)号:US20230325320A1

    公开(公告)日:2023-10-12

    申请号:US18185058

    申请日:2023-03-16

    Inventor: DAVID A. ROBERTS

    Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

    METHOD AND APPARATUS FOR CONTROLLING CACHE LINE STORAGE IN CACHE MEMORY

    公开(公告)号:US20220138103A1

    公开(公告)日:2022-05-05

    申请号:US17575461

    申请日:2022-01-13

    Inventor: DAVID A. ROBERTS

    Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

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