公开(公告)号：US20190163656A1

公开(公告)日：2019-05-30

申请号：US15826065

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Eric Christopher MORTON ,  Elizabeth COOPER ,  William L. WALKER ,  Douglas Benson HUNT ,  Richard Martin BORN ,  Richard H. Lee ,  Paul C. MIRANDA ,  Philip NG ,  Paul MOYER

IPC: G06F13/28 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0815 ,  G06F12/0893

CPC classification number: G06F13/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

公开(公告)号：US20210056042A1

公开(公告)日：2021-02-25

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu ARORA ,  Paul BLINZER ,  Philip NG ,  Nippon Harshadk RAVAL

IPC: G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US20240264969A1

公开(公告)日：2024-08-08

申请号：US18163620

申请日：2023-02-02

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC.

Inventor： BUHENG XU ,  Dong YU ,  Philip NG ,  Lianji CHENG

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.