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    Two-wire communication systems and applications
    1.
    发明授权
    Two-wire communication systems and applications 有权

    公开(公告)号：US11238004B2

    公开(公告)日：2022-02-01

    申请号：US16859611

    申请日：2020-04-27

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

    IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

    Clock sustain in the absence of a reference clock in a communication system
    2.
    发明授权
    Clock sustain in the absence of a reference clock in a communication system 有权

    公开(公告)号：US10250376B2

    公开(公告)日：2019-04-02

    申请号：US15411801

    申请日：2017-01-20

    Applicant: Analog Devices, Inc.

    Inventor： William Hooper ,  Lewis F. Lahr

    IPC: H04J3/06 ,  H04L7/00 ,  H04L7/04 ,  H04R5/00 ,  G06F13/30 ,  H04H60/00 ,  H04L12/40 ,  G06F13/362 ,  H04L12/403

    Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

    DIFFERENTIAL DECODER
    3.
    发明申请
    DIFFERENTIAL DECODER 有权
    差分解码器

    公开(公告)号：US20150009050A1

    公开(公告)日：2015-01-08

    申请号：US14191556

    申请日：2014-02-27

    Applicant: ANALOG DEVICES, INC.

    Inventor： Lewis F. Lahr ,  William J. Thomas ,  William Hooper

    IPC: H03M5/12

    CPC classification number: H03M5/12

    Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

    Abstract translation: 在一个示例性实施例中，公开了一种信号处理器，其被配置为对时钟优先的零切换差分曼彻斯特编码数据流进行解码。 数据流没有本地时钟，组合和顺序逻辑都用于将流解码为时钟数据信号和可选的错误信号。 解码包括将输入数据流分离成中间数据信号，中间时钟信号和调理信号的解析器。 数据和误差发生器接收三个信号并输出​​时钟数据信号和时钟误差信号。

    Differential decoder
    5.
    发明授权
    Differential decoder 有权
    差分解码器

    公开(公告)号：US09059724B2

    公开(公告)日：2015-06-16

    申请号：US14191556

    申请日：2014-02-27

    Applicant: Analog Devices, Inc.

    Inventor： Lewis F. Lahr ,  William J. Thomas ,  William Hooper

    IPC: H03M7/30 ,  H03M5/12

    CPC classification number: H03M5/12

    Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

    Abstract translation: 在一个示例性实施例中，公开了一种信号处理器，其被配置为对时钟优先的零切换差分曼彻斯特编码数据流进行解码。 数据流没有本地时钟，组合和顺序逻辑都用于将流解码为时钟数据信号和可选的错误信号。 解码包括将输入数据流分离成中间数据信号，中间时钟信号和调理信号的解析器。 数据和误差发生器接收三个信号并输出​​时钟数据信号和时钟误差信号。

    TWO-WIRE COMMUNICATION PROTOCOL ENGINE
    6.
    发明申请
    TWO-WIRE COMMUNICATION PROTOCOL ENGINE 有权
    双线通信协议发动机

    公开(公告)号：US20140101351A1

    公开(公告)日：2014-04-10

    申请号：US14063886

    申请日：2013-10-25

    Applicant: ANALOG DEVICES, INC.

    Inventor： William Hooper ,  Martin Kessler ,  Lewis F. Lahr ,  Michael Giancioppo

    IPC: G06F13/42 ,  G06F13/364

    CPC classification number: G06F13/42 ,  G06F13/364 ,  G06F13/4256 ,  G06F13/4273 ,  H04B3/50 ,  H04L1/16 ,  H04L2001/0093

    Abstract: In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.

    Abstract translation: 在示例实施例中，双线通信协议引擎管理双向多节点总线系统中的控制和数据传输，其中每个节点通过双绞线总线连接到另一节点。 一些实施例包括允许跨系统同步更新配置数据的状态机，分布式中断系统，基于系统中使用的数据编码的同步模式，以及应用于通过绞线传输的数据的一部分的数据加扰 对公车。 多节点总线系统包括主节点和多个从节点。 从节点可以通过双绞线对总线供电。

    Communication systems with serial peripheral interface functionality
    8.
    发明授权
    Communication systems with serial peripheral interface functionality 有权

    公开(公告)号：US11409690B2

    公开(公告)日：2022-08-09

    申请号：US17110126

    申请日：2020-12-02

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Lewis F. Lahr ,  William Hooper

    IPC: G06F13/42

    Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

    Communication systems with serial peripheral interface functionality
    9.
    发明授权
    Communication systems with serial peripheral interface functionality 有权

    公开(公告)号：US10884972B2

    公开(公告)日：2021-01-05

    申请号：US16406329

    申请日：2019-05-08

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Lewis F. Lahr ,  William Hooper

    IPC: G06F13/42

    Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

    Two-wire communication systems and applications
    10.
    发明授权
    Two-wire communication systems and applications 有权

    公开(公告)号：US10649948B2

    公开(公告)日：2020-05-12

    申请号：US16427131

    申请日：2019-05-30

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Miguel Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

    IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

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