公开(公告)号：US10311010B2

公开(公告)日：2019-06-04

申请号：US14884900

申请日：2015-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： Martin Kessler ,  Miguel Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G06F13/364 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418 ,  H04B3/54 ,  H04L12/403 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US11238004B2

公开(公告)日：2022-02-01

申请号：US16859611

申请日：2020-04-27

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US11874791B2

公开(公告)日：2024-01-16

申请号：US17589715

申请日：2022-01-31

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F1/266 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04L12/4035 ,  H04B2203/547 ,  H04R29/007 ,  Y02D10/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US10649948B2

公开(公告)日：2020-05-12

申请号：US16427131

申请日：2019-05-30

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.