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    AUXILIARY COMMUNICATION OVER A PULSE DENSITY MODULATED INTERFACE
    1.
    发明公开
    AUXILIARY COMMUNICATION OVER A PULSE DENSITY MODULATED INTERFACE 审中-公开

    公开(公告)号：US20230370311A1

    公开(公告)日：2023-11-16

    申请号：US18029011

    申请日：2021-09-30

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Lewis F. Lahr

    IPC: H04L27/00

    CPC classification number: H04L27/0008

    Abstract: Aspects of the embodiments are directed to auxiliary communication over a pulse density modulated (PDM) interface. Systems utilize a PDM interface between a sigma-delta modulator and a decimation filter to transmit data between devices. In some examples, the PDM interface is used to add non-PDM coded data communication between devices. Devices having a sigma-delta modulator can include microphones and accelerometers. Devices having a decimator can include digital signal processors (DSPs), microcontrollers, and audio codecs. In some examples, non-PDM coded data can be communicated between microphones and a node in a two-wire communication system, between a microphone and a digital signal processor (DSP), or between two microphones.

    Two-wire communication systems and applications
    2.
    发明授权
    Two-wire communication systems and applications 有权

    公开(公告)号：US11238004B2

    公开(公告)日：2022-02-01

    申请号：US16859611

    申请日：2020-04-27

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

    IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

    DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS
    6.
    发明申请
    DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS 有权
    通过双线通信总线进行分布式音频协调

    公开(公告)号：US20160034417A1

    公开(公告)日：2016-02-04

    申请号：US14884947

    申请日：2015-10-16

    Applicant: ANALOG DEVICES, INC.

    Inventor： Miguel Chavez ,  Martin Kessler

    IPC: G06F13/42 ,  G06F1/26 ,  G06F13/364

    CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04B2203/547 ,  H04L12/4035 ,  H04R29/007 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device.

    Abstract translation: 本文公开了用于通过双线通信总线进行分布式音频协调的系统和技术。 例如，在一些实施例中，第一从设备可以包括用于通过二线总线接收用于耦合到第二从设备的第二音频设备的同步控制帧，音频数据和动态处理器（DP）参数的电路 。 第一从设备可以包括从同步控制帧导出定时信息的电路，以及向耦合到第一从站的第一音频设备提供音频数据和DP参数（基于第二音频设备的DP参数）的电路 设备。

    TWO-WIRE COMMUNICATION PROTOCOL ENGINE
    9.
    发明申请
    TWO-WIRE COMMUNICATION PROTOCOL ENGINE 有权
    双线通信协议发动机

    公开(公告)号：US20140101351A1

    公开(公告)日：2014-04-10

    申请号：US14063886

    申请日：2013-10-25

    Applicant: ANALOG DEVICES, INC.

    Inventor： William Hooper ,  Martin Kessler ,  Lewis F. Lahr ,  Michael Giancioppo

    IPC: G06F13/42 ,  G06F13/364

    CPC classification number: G06F13/42 ,  G06F13/364 ,  G06F13/4256 ,  G06F13/4273 ,  H04B3/50 ,  H04L1/16 ,  H04L2001/0093

    Abstract: In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.

    Abstract translation: 在示例实施例中，双线通信协议引擎管理双向多节点总线系统中的控制和数据传输，其中每个节点通过双绞线总线连接到另一节点。 一些实施例包括允许跨系统同步更新配置数据的状态机，分布式中断系统，基于系统中使用的数据编码的同步模式，以及应用于通过绞线传输的数据的一部分的数据加扰 对公车。 多节点总线系统包括主节点和多个从节点。 从节点可以通过双绞线对总线供电。

    Systems and techniques for remote bus enable
    10.
    发明授权
    Systems and techniques for remote bus enable 有权

    公开(公告)号：US12164456B2

    公开(公告)日：2024-12-10

    申请号：US15684522

    申请日：2017-08-23

    Applicant: Analog Devices, Inc.

    Inventor： Martin Kessler

    IPC: G06F13/42 ,  G06F13/40

    Abstract: Disclosed herein are systems and techniques for remote bus enable. In some embodiments, a communication system with remote enable functionality may include: a master transceiver coupled to a downstream link of a bus; a voltage regulator, wherein the voltage regulator has a voltage output and an enable input, and the voltage output is coupled to the master transceiver; and a switch coupled to the enable input of the voltage regulator.

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