公开(公告)号：US11157277B2

公开(公告)日：2021-10-26

申请号：US16561430

申请日：2019-09-05

申请人： Arm Limited

发明人： Cedric Denis Robert Airaud ,  Albin Pierrick Tonnerre ,  Luca Nassi ,  Remi Marius Teyssier

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions of the system register and to copy the contents of the second one of the banked versions of the system register to the architectural register representing the given system register.

公开(公告)号：US11010159B2

公开(公告)日：2021-05-18

申请号：US16118528

申请日：2018-08-31

申请人： Arm Limited

发明人： Xiaoyang Shen ,  Cedric Denis Robert Airaud ,  Luca Nassi ,  Damien Robin Martin

IPC分类号： G06F9/30 ,  G06F5/01

摘要： Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the respective count operation stage, in which the bit-shifted data word for one bit-shift stage in the succession of processing stages is used as the data word to be processed by the next bit-shift stage in the succession of processing stages.

公开(公告)号：US10198267B2

公开(公告)日：2019-02-05

申请号：US15088368

申请日：2016-04-01

申请人： ARM LIMITED

发明人： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC分类号： G06F9/38

摘要： An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

公开(公告)号：US20160350114A1

公开(公告)日：2016-12-01

申请号：US15088368

申请日：2016-04-01

申请人： ARM LIMITED

发明人： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3863

摘要： An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

摘要翻译： 一种装置具有寄存器重命名电路，用于将由指令指定的架构寄存器说明符映射到识别物理寄存器的物理寄存器说明符。 恢复表识别架构寄存器说明符和先前映射的物理寄存器说明符之间的至少一个恢复映射。 寄存器保留电路指示一个或多个保留寄存器说明符。 响应于检测到当该指令或较旧的指令仍然可能读取寄存器时已经提交了对应于恢复映射的推测指令时，寄存器保留电路将该恢复映射的物理寄存器说明符指示为保留。

公开(公告)号：US09424045B2

公开(公告)日：2016-08-23

申请号：US13752621

申请日：2013-01-29

申请人： ARM LIMITED

发明人： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Frederic Claude Marie Piry ,  Albin Pierick Tonnerre

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

摘要： An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

摘要翻译： 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US10725964B2

公开(公告)日：2020-07-28

申请号：US16005790

申请日：2018-06-12

申请人： Arm Limited

发明人： Cedric Denis Robert Airaud ,  Luca Nassi ,  Damien Robin Martin ,  Xiaoyang Shen

IPC分类号： G06F15/80 ,  G06F1/3293 ,  G06F9/30 ,  G06F9/38

摘要： Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster. When the issuance target is the first data processing cluster, to schedule the first and second parts of the decoded SIMD instruction in series.

公开(公告)号：US10545764B2

公开(公告)日：2020-01-28

申请号：US15082601

申请日：2016-03-28

申请人： ARM LIMITED

发明人： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC分类号： G06F9/38

摘要： A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

公开(公告)号：US09361111B2

公开(公告)日：2016-06-07

申请号：US13737153

申请日：2013-01-09

申请人： ARM LIMITED

发明人： Luca Scalabrino ,  Melanie Emanuelle Lucie Teyssier ,  Cedric Denis Robert Airaud ,  Guillaume Schon

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

摘要： First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

摘要翻译： 第一处理电路处理程序指令流的至少一部分。 第一处理电路具有用于存储用于将体系结构寄存器说明符映射到物理寄存器说明符的数据和寄存器重命名电路的寄存器。 重命名数据存储存储用于识别架构和物理寄存器说明符之间的寄存器映射的重命名条目。 至少一些重命名条目具有指示在生成先前计数值和生成计数值之间发生的推测点数的计数值。 推测点可以例如是分支操作或加载/存储操作。

公开(公告)号：US10042640B2

公开(公告)日：2018-08-07

申请号：US15076889

申请日：2016-03-22

申请人： ARM LIMITED

发明人： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/52 ,  G06F8/41

摘要： A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

公开(公告)号：US09400655B2

公开(公告)日：2016-07-26

申请号：US13847892

申请日：2013-03-20

申请人： ARM Limited

发明人： Guillaume Schon ,  Cedric Denis Robert Airaud ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

摘要翻译： 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。