公开(公告)号：US20200004551A1

公开(公告)日：2020-01-02

申请号：US16025116

申请日：2018-07-02

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Alexei FEDOROV

IPC: G06F9/38

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has processing circuitry for executing a sequence of instructions, and value prediction storage that comprises a plurality of entries, where each entry is used to identify a predicted result value for an instruction allocated to that entry. Dispatch circuitry maintains a record of pending instructions awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry for execution. The dispatch circuitry is arranged to enable at least one pending instruction to be speculatively executed by the processing circuitry using as a source operand a predicted result value provided by the value prediction storage. Allocation circuitry is arranged to apply a default allocation policy to identify a first instruction to be allocated an entry in the value prediction storage. However, the allocation circuitry is further responsive to a trigger condition to identify a dependent instruction whose result value will be dependent on the result value produced by executing the first instruction, and to then allocate an entry in the value prediction storage to store a predicted result value for the identified dependent instruction. Such an approach can enable performance improvements to be achieved through the use of predicted result values even in situations where the prediction accuracy of the predicted result value for the first instruction proves not to be that high, by instead enabling a predicted result value for the dependent instruction to be used to allow speculative execution of further dependent instructions.

公开(公告)号：US20150137864A1

公开(公告)日：2015-05-21

申请号：US14081900

申请日：2013-11-15

Applicant: ARM Limited

Inventor： Paul Nicholas WHATMOUGH ,  Shidhartha DAS ,  David Michael BULL

IPC: H03K5/135

CPC classification number: H03K5/135

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract translation: 电路延迟监视装置具有环形振荡器，具有多个延迟元件，信号转换通过环形振荡器的延迟元件传播，并且多个采样点分布在环形振荡器周围。 选择电路根据由精细采样电路产生的信号转换的当前位置的指示来选择M个转换计数器电路中的一个，其相关位置大于来自信号转换的当前位置的所述预定量。 输出产生电路然后根据由选择电路选择的转换计数器电路的采样计数值，环形振荡器内的信号转换的当前位置的指示以及相关的参考计数数据，生成参考时间段的计数指示 到参考时间段的开始。

公开(公告)号：US20200004547A1

公开(公告)日：2020-01-02

申请号：US16021178

申请日：2018-06-28

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Chiloda Ashan Senarath PATHIRANE ,  Alexei FEDOROV

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F21/64

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.

公开(公告)号：US20180138900A1

公开(公告)日：2018-05-17

申请号：US15568174

申请日：2016-03-03

Applicant: ARM LIMITED

Inventor： Shidhartha DAS ,  David Michael BULL

IPC: H03K5/1534 ,  H03K3/037

CPC classification number: H03K5/1534 ,  H03K3/037 ,  H03K3/0375

Abstract: A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). In particular, when the pulse signal is generated at least partly whilst the timing window indication signal is set, the pulse control circuitry (35) controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry (20). In contrast, when the pulse signal is entirely generated whilst the timing window indication signal (40) is cleared, the pulse control circuitry (35) controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry (20). This gives rise to significant area and energy consumption savings, whilst still allowing reliable detection of timing errors.

公开(公告)号：US20140068371A1

公开(公告)日：2014-03-06

申请号：US14079276

申请日：2013-11-13

Applicant: ARM Limited

Inventor： Shidhartha DAS ,  David Michael BULL ,  Emre OZER

IPC: G06F11/16

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：US20180152252A1

公开(公告)日：2018-05-31

申请号：US15577487

申请日：2016-04-15

Applicant: ARM LIMITED

Inventor： Paul Nicholas WHATMOUGH ,  George SMART ,  Shidhartha DAS ,  David Michael BULL

IPC: H04B13/00 ,  H04B1/3827

CPC classification number: H04B13/005 ,  H04B1/385

Abstract: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.

公开(公告)号：US20170177055A1

公开(公告)日：2017-06-22

申请号：US15308658

申请日：2015-03-13

Applicant: ARM LIMITED

Inventor： Paul Nicholas WHATMOUGH ,  David Michael BULL ,  Shidhartha DAS

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/324 ,  G06F1/08

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

公开(公告)号：US20160126960A1

公开(公告)日：2016-05-05

申请号：US14531479

申请日：2014-11-03

Applicant: ARM Limited

Inventor： Paul Nicholas WHATMOUGH ,  David Michael BULL

IPC: H03L7/08 ,  G04F10/00

CPC classification number: H03L7/102 ,  H03L7/0992 ,  H03L2207/06

Abstract: An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry. Consequently, the generator circuitry is able to produce an operating parameter signal that has been compensated for noise in the circuit.

Abstract translation: 提供了一种操作参数方法和电路，其产生被补偿噪声的操作参数信号。 这种操作参数电路包括控制回路电路，其从第一电源操作，以向从与第一电源分开的第二电源操作的功能电路提供操作参数信号。 控制回路电路包括基于输入信号产生操作参数信号的发生器电路。 复制发生器电路从第二电源操作以基于输入信号生成另外的操作参数信号。 调整电路对操作参数信号和其他操作参数信号进行比较，并根据比较结果产生调整后的输入信号。 经调整的输入信号由发生器电路接收。 因此，发电机电路能够产生已经补偿了电路中的噪声的工作参数信号。

公开(公告)号：US20230342298A1

公开(公告)日：2023-10-26

申请号：US17729233

申请日：2022-04-26

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Vincent REZARD ,  Anton ANTONOV

IPC: G06F12/0842 ,  G06F12/0891 ,  G06F9/38

CPC classification number: G06F12/0842 ,  G06F12/0891 ,  G06F9/3816 ,  G06F2212/1021

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

公开(公告)号：US20210279063A1

公开(公告)日：2021-09-09

申请号：US17158276

申请日：2021-01-26

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Frederic Claude Marie PIRY ,  Alexei FEDOROV

IPC: G06F9/38

Abstract: An apparatus has processing circuitry for executing instructions and fetch circuitry for fetching the instructions for execution. When a branch instruction is encountered by the fetch circuitry, it determines subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry. Value prediction circuitry is used to maintain a predicted result value for one or more instructions, and dispatch circuitry maintains a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry. When a given instruction whose predicted result value is maintained by the value prediction circuitry has a dependent instruction whose outcome is dependent on a result value of the given instruction, the dispatch circuitry nay be arranged to enable speculative execution of that dependent instruction using the predicted result value of the given instruction. Analysis circuitry is arranged, when the dependent instruction is the branch instruction, to detect a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate that the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction. On detection of the mispredict condition, a control signal is issued to indicate that the branch instruction has been mispredicted.