公开(公告)号：US10255195B2

公开(公告)日：2019-04-09

申请号：US15614644

申请日：2017-06-06

Applicant: ARM LIMITED

Inventor： Michal Karol Bogusz ,  Quinn Carter ,  Andrew Brookfield Swaine

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/1009

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

公开(公告)号：US10593305B2

公开(公告)日：2020-03-17

申请号：US15361751

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Michal Karol Bogusz ,  Damian Piotr Modrzyk ,  Quinn Carter ,  Thomas James Cooksey

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06T1/60 ,  G09G5/397 ,  G09G5/36 ,  G09G5/395 ,  G06T15/00

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

公开(公告)号：US10509743B2

公开(公告)日：2019-12-17

申请号：US15612072

申请日：2017-06-02

Applicant: ARM LIMITED

Inventor： Daren Croxford ,  Sharjeel Saeed ,  Quinn Carter ,  Michael Andrew Campbell

IPC: G06F13/16 ,  G06F13/00

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

公开(公告)号：US10466915B2

公开(公告)日：2019-11-05

申请号：US15636524

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries

IPC: G06F3/06 ,  H04N19/423

Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.

公开(公告)号：US20170162179A1

公开(公告)日：2017-06-08

申请号：US15361751

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Michal Karol Bogusz ,  Damian Piotr Modrzyk ,  Quinn Carter ,  Thomas James Cooksey

IPC: G09G5/397 ,  G09G5/36 ,  G06F12/1027 ,  G06F12/0862 ,  G06F12/0875

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

公开(公告)号：US10430099B2

公开(公告)日：2019-10-01

申请号：US15472637

申请日：2017-03-29

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries ,  Andreas Due Engh-Halstvedt

IPC: G06F3/06 ,  G09G5/393 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks.Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into.For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.

公开(公告)号：US20180004443A1

公开(公告)日：2018-01-04

申请号：US15636524

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries

IPC: G06F3/06

Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.

公开(公告)号：US20170285955A1

公开(公告)日：2017-10-05

申请号：US15472637

申请日：2017-03-29

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries ,  Andreas Due Engh-Halstvedt

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T2210/08 ,  G09G5/393 ,  G09G2360/12 ,  G09G2360/122

Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks.Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into.For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.