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公开(公告)号：US11664681B2
公开(公告)日：2023-05-30
申请号：US17364057
申请日：2021-06-30
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Sahan Sajeewa Hiniduma Udugama Gamage , Pranay Prabhat , Benoit Labbe , Thanusree Achuthan
CPC classification number: H02J50/001 , H02J50/20 , H02J50/40 , H02M3/07
Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.
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Patent Agency Ranking
公开(公告)号：US20220166436A1
公开(公告)日：2022-05-26
申请号：US17103585
申请日：2020-11-24
Applicant: Arm Limited
Inventor： Benoit Labbe , Shidhartha Das , Thanusree Achuthan
Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.
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3.发明申请公开(公告)号：US20180225402A9
公开(公告)日：2018-08-09
申请号：US14528314
申请日：2014-10-30
Applicant: ARM Limited
Inventor： Paul DE DOOD , Marlin Wayne Frederick, JR. , Jerry Chaoyuan Wang , Brian Douglas Ngai Lee , Brian Tracy Cline , Xiaoqing Xu , Andy Wangkun Chen , Yew Keong Chong , Tom Shore , Sriram Thyagarajan , Gus Yeung , Yanbin Jiang , Emmanuel Jean Marie Olivier Pacaud , Matthieu Domonique Henri Pauly , Sylvia Xiuhui Li , Thanusree Achuthan , Daniel J. Albers , David William Granda
IPC: G06F17/50
CPC classification number: G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081
Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.
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公开(公告)号：US20230006467A1
公开(公告)日：2023-01-05
申请号：US17364057
申请日：2021-06-30
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Sahan Sajeewa Hiniduma Udugama Gamage , Pranay Prabhat , Benoit Labbe , Thanusree Achuthan
Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.
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公开(公告)号：US11444625B2
公开(公告)日：2022-09-13
申请号：US17103585
申请日：2020-11-24
Applicant: Arm Limited
Inventor： Benoit Labbe , Shidhartha Das , Thanusree Achuthan
Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.
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公开(公告)号：US10083269B2
公开(公告)日：2018-09-25
申请号：US14528314
申请日：2014-10-30
Applicant: ARM Limited
Inventor： Paul De Dood , Marlin Wayne Frederick , Jerry Chaoyuan Wang , Brian Douglas Ngai Lee , Brian Tracy Cline , Xiaoqing Xu , Andy Wangkun Chen , Yew Keong Chong , Tom Shore , Sriram Thyagarajan , Gus Yeung , Yanbin Jiang , Emmanuel Jean Marie Olivier Pacaud , Matthieu Domonique Henri Pauly , Sylvia Xiuhui Li , Thanusree Achuthan , Daniel J. Albers , David William Granda
IPC: G06F17/50
CPC classification number: G06F17/5068 , G06F17/5045 , G06F17/5072 , G06F17/5077 , G06F17/5081
Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.
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