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    POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE
    2.
    发明申请
    POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE 有权

    公开(公告)号：US20250103129A1

    公开(公告)日：2025-03-27

    申请号：US18474400

    申请日：2023-09-26

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar ,  Vivek Asthana ,  Andrew John Turner ,  Alex James Waugh

    IPC: G06F1/3296 ,  G06F12/0815

    Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

    Bypass Circuitry for Memory Applications
    4.
    发明申请
    Bypass Circuitry for Memory Applications 审中-公开

    公开(公告)号：US20190267049A1

    公开(公告)日：2019-08-29

    申请号：US15904292

    申请日：2018-02-23

    Applicant: Arm Limited

    Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

    IPC: G11C7/06 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

    Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

    Buried Metal Techniques for Memory Applications
    6.
    发明公开
    Buried Metal Techniques for Memory Applications 审中-公开

    公开(公告)号：US20240153551A1

    公开(公告)日：2024-05-09

    申请号：US17980335

    申请日：2022-11-03

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Vivek Asthana ,  Sony ,  Ettore Amirante ,  Yew Keong Chong

    IPC: G11C11/418

    CPC classification number: G11C11/418

    Abstract: Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.

    Bypass circuitry for memory applications
    7.
    发明授权
    Bypass circuitry for memory applications 有权

    公开(公告)号：US10418124B1

    公开(公告)日：2019-09-17

    申请号：US15904292

    申请日：2018-02-23

    Applicant: Arm Limited

    Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

    IPC: G11C7/06 ,  G11C29/00 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12 ,  G11C29/56 ,  G11C29/28 ,  G11C16/04 ,  G11C29/12 ,  G11C29/14

    Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

    Dummy Wordline Underdrive Circuitry
    8.
    发明申请
    Dummy Wordline Underdrive Circuitry 审中-公开

    公开(公告)号：US20190066769A1

    公开(公告)日：2019-02-28

    申请号：US15690562

    申请日：2017-08-30

    Applicant: ARM Limited

    Inventor： Vivek Asthana ,  Nitin Jindal ,  Nikhil Kaushik ,  Kapil Mittal ,  Divyank Gupta ,  Shakir Malik ,  Stefi Bhavsar

    IPC: G11C11/418 ,  H01L27/11

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.

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