公开(公告)号：US12293092B2

公开(公告)日：2025-05-06

申请号：US18083306

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

IPC: G06F3/06

Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

公开(公告)号：US11995351B2

公开(公告)日：2024-05-28

申请号：US17515976

申请日：2021-11-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L Greathouse ,  Sean Keely ,  Alan D. Smith ,  Anthony Asaro ,  Ling-Ling Wang ,  Milind N Nemlekar ,  Hari Thangirala ,  Felix Kuehling

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US20230384947A1

公开(公告)日：2023-11-30

申请号：US18208639

申请日：2023-06-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. Greathouse ,  Alan D. Smith ,  Francisco L. Duran ,  Felix Kuehling ,  Anthony Asaro

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F12/0607 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0644

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

公开(公告)号：US11100604B2

公开(公告)日：2021-08-24

申请号：US16263709

申请日：2019-01-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jeffrey Gongxian Cheng ,  Ahmed M. Abdelkhalek ,  Yinan Jiang ,  Xingsheng Wan ,  Anthony Asaro ,  David Martinez Nieto

IPC: G06F15/80 ,  G06T1/20 ,  G06F9/38 ,  G06F9/48 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

公开(公告)号：US20200250787A1

公开(公告)日：2020-08-06

申请号：US16263709

申请日：2019-01-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jeffrey Gongxian Cheng ,  Ahmed M. Abdelkhalek ,  Yinan Jiang ,  Xingsheng Wan ,  Anthony Asaro ,  David Martinez Nieto

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/38

Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

公开(公告)号：US20200042348A1

公开(公告)日：2020-02-06

申请号：US16050948

申请日：2018-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F12/1009 ,  G06F12/14 ,  G06F9/52 ,  G06F9/54 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US10545800B2

公开(公告)日：2020-01-28

申请号：US15610047

申请日：2017-05-31

Applicant: ATI Technologies ULC

Inventor： Anthony Asaro ,  Gongxian Jeffrey Cheng

IPC: G06F9/52 ,  G06F9/54 ,  G06F9/50 ,  G06F9/46 ,  G06F9/455 ,  G06F9/48

Abstract: A technique for facilitating direct doorbell rings in a virtualized system is provided. A first device is configured to “ring” a “doorbell” of a second device, where both the first and second devices are not a host processor such as a central processing unit and are coupled to an interconnect fabric such as peripheral component interconnect express (“PCIe”). The first device is configured to ring the doorbell of the second device by writing to a doorbell address in a guest physical address space. For security reasons, a check block checks an offset portion of the doorbell address against a set of allowed doorbell addresses for doorbells specified in the guest physical address space, allowing the doorbell to be written if the doorbell is included in the set of allowed doorbell addresses.

公开(公告)号：US10365824B2

公开(公告)日：2019-07-30

申请号：US15495296

申请日：2017-04-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Anthony Asaro

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027

Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.

公开(公告)号：US20180173649A1

公开(公告)日：2018-06-21

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/4068

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

公开(公告)号：US09910788B2

公开(公告)日：2018-03-06

申请号：US14861055

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro

IPC: G06F12/121 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/12 ,  G06F12/127 ,  G06F13/28 ,  G06F2212/656

Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.