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公开(公告)号：US20170263653A1
公开(公告)日：2017-09-14
申请号：US15457197
申请日：2017-03-13
Applicant: AU Optronics Corporation
Inventor： Ssu-Hui LU , Chih-Chung SU , Ming-Hsien LEE
CPC classification number: H01L27/1248 , G02F1/136227 , G02F2001/134372 , H01L27/1225 , H01L27/124 , H01L27/1244 , H01L27/156
Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.
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公开(公告)号：US20210158741A1
公开(公告)日：2021-05-27
申请号：US17168452
申请日：2021-02-05
Applicant: AU Optronics Corporation
Inventor： Che-Chia CHANG , Ming-Hsien LEE , Chun-Fu CHUNG , Ming-Hung CHUANG
IPC: G09G3/20
Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.
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公开(公告)号：US20150028336A1
公开(公告)日：2015-01-29
申请号：US14486069
申请日：2014-09-15
Applicant: AU Optronics Corporation
Inventor： Jia-Hong YE , Ssu-Hui LU , Wu-Hsiung LIN , Chao-Chien CHIU , Ming-Hsien LEE , Chia-Tien PENG , Wei-Ming HUANG
IPC: H01L27/12
CPC classification number: H01L27/1255 , H01L27/1218 , H01L27/1248 , H01L29/78603
Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.
Abstract translation: 有源器件阵列衬底包括柔性衬底，栅电极，电介质层，沟道层，源电极，漏电极和像素电极。 柔性基板具有彼此相邻的晶体管区域和透明区域。 栅电极设置在晶体管区域上。 电介质层覆盖柔性基板和栅电极。 布置在栅电极上的介电层的一部分具有第一厚度。 布置在透明区域上的介电层的另一部分具有小于第一厚度的第二厚度。 沟道层设置在栅电极的上方。 源电极和漏极电连接到沟道层。 像素电极设置在布置在透明区域上的电介质层上。 像素电极电连接到漏电极。
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公开(公告)号：US20220036809A1
公开(公告)日：2022-02-03
申请号：US17320413
申请日：2021-05-14
Applicant: AU Optronics Corporation
Inventor： Chia-En WU , Ming-Hsien LEE , Wei-Chia CHIU , Kuan-Yu CHEN , Chia-Yen LIN
IPC: G09G3/32
Abstract: A pixel driving device includes a capacitance, a reset circuit, a compensation circuit, a driving transistor and a first transistor. Reset circuit and compensation circuit are coupled to a first end and a second end of capacitance. First transistor is coupled between second end of driving transistor and second end of capacitance. Reset circuit resets first end of capacitance at a power supply voltage and reset second end of capacitance at a reference voltage according to a first sweep signal respectively. Compensation circuit writes a data voltage into first end of capacitance via driving transistor and second end of capacitance is maintained at reference voltage according to a second sweep signal. First transistor generates a driving voltage difference between first end and second end of capacitance according to a control signal. Driving transistor outputs a current to a luminous element according to driving voltage difference.
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公开(公告)号：US20180315389A1
公开(公告)日：2018-11-01
申请号：US15953720
申请日：2018-04-16
Applicant: AU Optronics Corporation
Inventor： Kai-Wei HONG , Chun-Da TU , Ming-Hsien LEE , Chuang-Cheng YANG , Yi-Cheng LIN , Chun-Feng LIN
CPC classification number: G09G3/3677 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/06 , G11C19/28 , G11C19/287
Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.
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Patent Agency Ranking
公开(公告)号：US20210134211A1
公开(公告)日：2021-05-06
申请号：US16920463
申请日：2020-07-03
Applicant: AU Optronics Corporation
Inventor： Chia-En WU , Ming-Hsien LEE , Wei-Chia CHIU , Kuan-Yu CHEN
Abstract: A pixel circuit including a driving transistor, a light emission element, a compensation circuit, a storage capacitor, and a writing circuit is provided. The light emission control circuit is configured to selectively conduct the light emission element to the driving transistor. The compensation circuit is coupled with the light emission control circuit and a control terminal of the driving transistor, and is configured to form a diode-connected structure with the driving transistor. The storage capacitor includes a first terminal and a second terminal. The first terminal of the storage capacitor is coupled with the control terminal of the driving transistor, and the light emission control circuit is configured to selectively conduct the second terminal of the storage capacitor to a first power terminal. The writing circuit is configured to provide different voltages to the first terminal of the storage capacitor and the second terminal of the storage capacitor.
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公开(公告)号：US20200160776A1
公开(公告)日：2020-05-21
申请号：US16415454
申请日：2019-05-17
Applicant: AU Optronics Corporation
Inventor： Ming-Hsien LEE , Yi-Cheng LIN , Chuang-Cheng YANG , Kai-Wei HONG , Chun-Feng LIN
IPC: G09G3/32
Abstract: A driving circuit includes a first driving switch, a second driving switch and a current regulating unit. The first driving switch is electrically connected to a first power source and a first light emitting element. When the first driving switch is turned on, the first driving switch is configured to receive a first current. The second driving switch is electrically connected to a second power source and a second light emitting element. When the second driving switch is turned on, the second driving switch is configured to receive a second current. The current regulating unit is electrically connected to a negative terminal of the second light emitting element and a positive terminal of the first light emitting element. When the current regulating unit is disabled, the second current sequentially flows through the second light emitting element and the first light emitting element.
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公开(公告)号：US20200090614A1
公开(公告)日：2020-03-19
申请号：US16690606
申请日：2019-11-21
Applicant: AU Optronics Corporation
Inventor： Kai-Wei HONG , Chun-Da TU , Ming-Hsien LEE , Chuang-Cheng YANG , Yi-Cheng LIN , Chun-Feng LIN
Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.
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公开(公告)号：US20190043412A1
公开(公告)日：2019-02-07
申请号：US15864498
申请日：2018-01-08
Applicant: AU OPTRONICS CORPORATION
Inventor： Chuang-Cheng YANG , Chun-Feng LIN , Ming-Hsien LEE , Kai-Wei HONG , Chun-Da TU , Yi-Cheng LIN
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G3/3677 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/08
Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n−1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.
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公开(公告)号：US20180151601A1
公开(公告)日：2018-05-31
申请号：US15488629
申请日：2017-04-17
Applicant: AU Optronics Corporation
Inventor： Ming-Hsien LEE
IPC: H01L27/12 , G02F1/1362 , G02F1/1333 , G02F1/1368
CPC classification number: H01L27/1248 , G02F1/133345 , G02F1/136209 , G02F1/136227 , G02F1/1368 , G02F2001/133357 , G02F2201/123 , H01L27/1218 , H01L27/124 , H01L29/78603 , H01L29/78621 , H01L29/78636
Abstract: A pixel structure is disposed on a substrate and includes a bump, a first insulating layer, a semiconductive layer, a second insulating layer, a metal layer, and a pixel electrode. The bump is disposed on the substrate. The first insulating layer is disposed on the substrate and covers the bump. The first insulating layer has a protruding portion at the position at which the first insulating layer covers the bump. The semiconductive layer is disposed on the first insulating layer, and at least a portion of the semiconductive layer is disposed above the protruding portion. The second insulating layer is disposed on the first insulating layer and covers the semiconductive layer. The second insulating layer has a via, so as to make a portion of the semiconductive layer be not covered by the second insulating layer. The via corresponds to the protruding portion in a direction perpendicular to the substrate. The metal layer is electrically connected to the semiconductive layer through the via.
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