公开(公告)号：US09450078B1

公开(公告)日：2016-09-20

申请号：US14678874

申请日：2015-04-03

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Daniel Tang ,  Zhimin Wan ,  Ching-I Li ,  Ger-Pin Lin

IPC: H01L21/38 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/1083

Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Abstract translation: 在鳍状场效应晶体管（finFET）器件中形成穿通停止区域时，可蚀刻衬底以形成限定翅片结构的一对沟槽。 第一剂量的离子的一部分可以通过每个沟槽的底壁注入到衬底中，以形成至少部分地延伸在翅片结构的沟道区域下面的一对第一掺杂区域。 可以蚀刻每个沟槽的底壁处的衬底以增加每个沟槽的深度。 在每个沟槽的底壁处蚀刻衬底可以去除每个沟槽下的每个第一掺杂剂区域的一部分。 翅片结构下面的一对第一掺杂剂区域的剩余部分可以至少部分地限定finFET器件的穿通阻挡区域。

公开(公告)号：US09209278B2

公开(公告)日：2015-12-08

申请号：US14195712

申请日：2014-03-03

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Daniel Tang ,  Tzu-Shih Yen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/165 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract translation: 形成具有在源极区和漏极区之间具有源极区，漏极区和沟道区的鳍的finFET。 翅片在半导体晶片上蚀刻。 形成具有与沟道区域直接接触的绝缘层和与绝缘层直接接触的导电栅极材料的栅极堆叠。 蚀刻源极和漏极区域，离开鳍片的沟道区域。 外延半导体在与源极和漏极区相邻的沟道区的侧面生长以形成源外延区和漏极外延区。 源极和漏极外延区域在生长外延半导体的同时原位掺杂。

公开(公告)号：US09006065B2

公开(公告)日：2015-04-14

申请号：US13648127

申请日：2012-10-09

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Tzu-Shih Yen ,  Daniel Tang ,  Tsungnan Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L27/12 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/2236 ,  H01L29/66803 ,  H01L29/785

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract translation: 在等离子体掺杂非平面半导体器件中，获得其上形成有非平面半导体体的衬底。 具有非平面半导体本体的基板可以放置在室中。 等离子体可以在室中形成，等离子体可以含有掺杂离子。 可以产生第一偏置电压以将掺杂剂离子注入到非平面半导体本体的区域中。 可以产生第二偏置电压以将掺杂剂离子注入到相同的区域中。 在一个示例中，第一偏置电压和第二偏置电压可以不同。