公开(公告)号：US09214199B2

公开(公告)日：2015-12-15

申请号：US14497977

申请日：2014-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

IPC: G06F12/00 ,  G11C7/00 ,  G11C29/02 ,  G06F3/06 ,  G06F13/16 ,  G06F12/16 ,  G11C11/40

CPC classification number: G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。

公开(公告)号：US20150078104A1

公开(公告)日：2015-03-19

申请号：US14497977

申请日：2014-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。