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    Chiplet-Level Performance Information for Configuring Chiplets in a Processor
    2.
    发明公开
    Chiplet-Level Performance Information for Configuring Chiplets in a Processor 审中-公开

    公开(公告)号：US20230153218A1

    公开(公告)日：2023-05-18

    申请号：US17526218

    申请日：2021-11-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shrikanth Ganapathy ,  Yasuko Eckert ,  Anthony Gutierrez ,  Karthik Ramu Sangaiah ,  Vedula Venkata Srikant Bharadwaj

    IPC: G06F11/30 ,  G06F15/80

    CPC classification number: G06F11/3051 ,  G06F15/80 ,  G06F11/3024

    Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.

    SYSTEMS AND METHODS FOR MODEL ENSEMBLE ACCELERATION
    3.
    发明申请
    SYSTEMS AND METHODS FOR MODEL ENSEMBLE ACCELERATION 有权

    公开(公告)号：US20250111195A1

    公开(公告)日：2025-04-03

    申请号：US18478639

    申请日：2023-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Karthik Ramu Sangaiah ,  Yao Cui Fehlis

    IPC: G06N3/045 ,  G06N3/063

    Abstract: Disclosed is a computer-implemented method for model ensemble acceleration in an active learning loop. The method includes receiving a set of datapoint inputs, where each datapoint input is an unlabeled equivalent of other datapoint inputs in the set of datapoint inputs and has a different applied weight value. The method then executes a set of neural network models, where the execution of each neural network model is based on the received set of datapoint inputs. The outputs from the set of neural network models are analyzed, where an inference computation is performed, and a label for the set of datapoints is determined. The method then stores the labeled set of datapoint inputs in a database. Various other methods, systems, and computer-readable media are also disclosed.

    Accelerating relaxed remote atomics on multiple writer operations
    4.
    发明授权
    Accelerating relaxed remote atomics on multiple writer operations 有权

    公开(公告)号：US12105957B2

    公开(公告)日：2024-10-01

    申请号：US18087964

    申请日：2022-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.

    VLIW power management
    5.
    发明授权
    VLIW power management 有权

    公开(公告)号：US11816490B2

    公开(公告)日：2023-11-14

    申请号：US17550878

    申请日：2021-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anthony Thomas Gutierrez ,  Karthik Ramu Sangaiah ,  Vedula Venkata Srikant Bharadwaj

    IPC: G06F9/38 ,  G06F1/18 ,  G06F9/30

    CPC classification number: G06F9/3853 ,  G06F1/189 ,  G06F9/30145 ,  G06F9/3885

    Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.

    ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS
    8.
    发明公开
    ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS 审中-公开

    公开(公告)号：US20240211134A1

    公开(公告)日：2024-06-27

    申请号：US18087964

    申请日：2022-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.

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