公开(公告)号：US20220181268A1

公开(公告)日：2022-06-09

申请号：US17111350

申请日：2020-12-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Meng-Wei HSIEH ,  Yu-Pin TSAI

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/31

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

公开(公告)号：US20210202409A1

公开(公告)日：2021-07-01

申请号：US16732154

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN

IPC: H01L23/66 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.

公开(公告)号：US20210090965A1

公开(公告)日：2021-03-25

申请号：US16578088

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Hsu-Chiang SHIH ,  Cheng-Yuan KUNG ,  Hung-Yi LIN

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

公开(公告)号：US20190057809A1

公开(公告)日：2019-02-21

申请号：US15680059

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Teck-Chong LEE ,  Sheng-Chi HSIEH ,  Chien-Hua CHEN

IPC: H01F27/40 ,  H01F21/12 ,  H01F27/28 ,  H01F27/29 ,  H03H7/38 ,  H01L25/16

Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.

公开(公告)号：US20240304555A1

公开(公告)日：2024-09-12

申请号：US18119272

申请日：2023-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Yi LIN ,  Cheng-Yuan KUNG

IPC: H01L23/538 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L23/5381 ,  H01L23/49811 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16148 ,  H01L2224/16225

Abstract: A package structure and a method for manufacturing the package structure are provided. The package structure includes an interposer, a first electronic component over the interposer, and a second electronic component over the interposer. The interposer includes a first interconnector and a second interconnector. The first electronic component and the second electronic component are disposed at a first horizontal level and electrically connected to each other through the first interconnector. The second interconnector is electrically connected to a third electronic component disposed at a second horizontal level different from the first horizontal level.

公开(公告)号：US20230215816A1

公开(公告)日：2023-07-06

申请号：US17566575

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hsu-Chiang SHIH ,  Hung-Yi LIN ,  Chien-Mei HUANG

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1511 ,  H01L2924/3512

Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

公开(公告)号：US20230075336A1

公开(公告)日：2023-03-09

申请号：US17987693

申请日：2022-11-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Cheng-Yuan KUNG

IPC: H01L25/10 ,  H01L41/047 ,  H01L41/053 ,  H03H9/64 ,  H01L41/23 ,  H01L41/25 ,  H03H9/60 ,  H01L23/522

Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.

公开(公告)号：US20220148974A1

公开(公告)日：2022-05-12

申请号：US17584051

申请日：2022-01-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN

IPC: H01L23/538 ,  H01L25/10

Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section. The second signal transmission path is between the second surface of the sub-computing section and the at least one conductive via of the sub-computing section.

公开(公告)号：US20180337164A1

公开(公告)日：2018-11-22

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Hung-Yi LIN ,  Cheng-Yuan KUNG ,  Teck-Chong LEE ,  Shiuan-Yu LIN

IPC: H01L25/16 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US20240413061A1

公开(公告)日：2024-12-12

申请号：US18207087

申请日：2023-06-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Cheng-Yuan KUNG ,  Yaohsin CHOU

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/18

Abstract: A package structure is provided. The package structure includes a substrate, a wiring structure, and a wire bundle structure. The wiring structure is over the substrate. The wire bundle structure is between the wiring structure and the substrate. The wire bundle structure includes a first wire bundle extending from the substrate and a second wire bundle extending from the wiring structure and contacting the first nanowire bundle. The wire bundle structure is configured to reduce a variation in a distance of a gap between the substrate and the wiring structure.