公开(公告)号：US20210379590A1

公开(公告)日：2021-12-09

申请号：US16893150

申请日：2020-06-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen LEE ,  Ying-Te OU ,  Chin-Cheng KUO ,  Chung Hao CHEN

IPC: B01L3/00 ,  H01L23/538

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

公开(公告)号：US20220384308A1

公开(公告)日：2022-12-01

申请号：US17334564

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen LEE ,  Hung-Yi LIN

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.

公开(公告)号：US20180122749A1

公开(公告)日：2018-05-03

申请号：US15340808

申请日：2016-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chih LEE ,  Chin-Cheng KUO ,  Yung-Hui WANG ,  Wei-Hong LAI ,  Chung-Ting WANG ,  Hsiao-Yen LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.