公开(公告)号：US20210379590A1

公开(公告)日：2021-12-09

申请号：US16893150

申请日：2020-06-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen LEE ,  Ying-Te OU ,  Chin-Cheng KUO ,  Chung Hao CHEN

IPC: B01L3/00 ,  H01L23/538

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

公开(公告)号：US20170200702A1

公开(公告)日：2017-07-13

申请号：US15404093

申请日：2017-01-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Ying-Te OU ,  Pao-Nan LEE

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

公开(公告)号：US20170365515A1

公开(公告)日：2017-12-21

申请号：US15184828

申请日：2016-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO ,  Pao-Nan LEE ,  Chih-Pin HUNG ,  Ying-Te OU

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/05 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05562

Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.

公开(公告)号：US20170287863A1

公开(公告)日：2017-10-05

申请号：US15628485

申请日：2017-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO ,  Ying-Te OU ,  Lu-Ming LAI

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/10156 ,  H01L2924/00014

Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.

公开(公告)号：US20160118325A1

公开(公告)日：2016-04-28

申请号：US14990425

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hui WANG ,  Ying-Te OU

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/185 ,  H05K1/188 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract translation: 嵌入式芯片基板包括第一绝缘层，芯层，芯片，第二绝缘层，第一电路层和第二电路层。 设置在第一绝缘层上的芯层具有露出第一绝缘层的一部分的开口。 芯片被粘合到由开口和第一绝缘层构成的凹槽中。 第二绝缘层设置在芯层上以覆盖芯片。 第一电路层设置在位于第一电路层和芯层之间的第一绝缘层的外侧。 第二电路层设置在位于第二电路层和芯层之间的第二绝缘层的外侧。 第一电路层电连接到电连接到芯片的第二电路层。