公开(公告)号：US09773753B1

公开(公告)日：2017-09-26

申请号：US15356400

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Ting Lin ,  Chi-Yu Wang ,  Wei-Hong Lai ,  Chin-Li Kao

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/14 ,  H01L2924/3511

Abstract: A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle θ1 relative to a direction of extension of the body portion.

公开(公告)号：US09478500B2

公开(公告)日：2016-10-25

申请号：US14624331

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Ching Chen ,  Chin-Li Kao ,  Hung-Jen Chang ,  Tang-Yuan Chen ,  Wei-Hong Lai

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/683 ,  H05K1/11

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K3/205 ,  H05K2201/10378

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

Abstract translation: 这里描述了用于翘曲控制的插入式衬底设计，包括所述插入器衬底的半导体结构及其制造方法。 插入器基板限定空腔并且还包括加强结构，其中加强结构用于控制半导体封装结构的翘曲。