公开(公告)号：US20230397342A1

公开(公告)日：2023-12-07

申请号：US18324632

申请日：2023-05-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masayuki Mizuno

IPC: H05K3/46 ,  H05K3/20 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K3/4644 ,  H05K3/205 ,  H05K1/112 ,  H01L23/49822 ,  H05K2201/09563

Abstract: A wiring board includes a first wiring layer, an insulating layer that is arranged on the first wiring layer, and a second wiring layer that is arranged on the insulating layer. The first wiring layer includes a first plain layer, an opening that penetrates through the first plain layer, and a reinforcing pad that is arranged in the opening. The second wiring layer includes a second plain layer. The insulating layer includes a reinforcing via that connects the reinforcing pad and the second plain layer.

公开(公告)号：US20180235089A1

公开(公告)日：2018-08-16

申请号：US15804207

申请日：2017-11-06

Applicant: OLYMPUS CORPORATION

Inventor： Kazuaki KOJIMA

IPC: H05K3/20 ,  H05K1/11 ,  H01L21/768 ,  H05K1/18 ,  H05K3/10 ,  H01L21/48 ,  H05K3/40

CPC classification number: H05K3/205 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/181 ,  H05K3/02 ,  H05K3/10 ,  H05K3/4038 ,  H05K3/4061 ,  H05K3/421 ,  H05K2201/09036 ,  H05K2203/0726

Abstract: For a wiring board, silicon including a first main surface and a second main surface is a base, a first conductor on the first main surface and a second conductor on the second main surface are connected by a through electrode formed of an electroplating layer disposed on an inner surface of a through hole, a bottom surface of which is the second conductor, and a hilling which is a continuous projecting portion is provided on the inner surface of the through hole from the first main surface to the second main surface in parallel with a depth direction.

公开(公告)号：US20180209046A1

公开(公告)日：2018-07-26

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K3/18 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46

CPC classification number: C23C18/1653 ,  C23C18/1605 ,  C23C18/1607 ,  C23C18/1657 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/115 ,  H05K3/184 ,  H05K3/205 ,  H05K3/244 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/10378

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US20180184518A1

公开(公告)日：2018-06-28

申请号：US15852950

申请日：2017-12-22

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Ryo Fukasawa

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L23/498 ,  H01L24/00 ,  H05K1/181 ,  H05K3/205 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/09118 ,  H05K2201/10674 ,  H05K2203/0323 ,  H05K2203/1316

Abstract: A wiring substrate includes a metal plate in which at least one wiring formation region is defined, a cavity formed in the wiring formation region, a concave part formed to have a frame shape at a peripheral edge portion of a bottom portion of the cavity, a first pad disposed at a central portion of the bottom portion of the cavity, a wiring portion connected to the first pad and disposed on and extended along the central portion of the bottom portion of the cavity, a side surface of the concave part and a bottom surface of the concave part, and a multi-layered wiring layer disposed at the central portion of the bottom portion of the cavity so as to cover the first pad and a part of the wiring portion. The multi-layered wiring layer has a second pad provided at an upper surface-side and connected to the wiring portion.

公开(公告)号：US09978705B2

公开(公告)日：2018-05-22

申请号：US15222873

申请日：2016-07-28

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/48 ,  H01L23/00 ,  H05K3/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

公开(公告)号：US20180054888A1

公开(公告)日：2018-02-22

申请号：US15681948

申请日：2017-08-21

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki ISHIHARA ,  Hiroyuki BAN ,  Haiying MEI

IPC: H05K1/02

CPC classification number: H05K1/0284 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K1/0296 ,  H05K3/007 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/10674

Abstract: A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the laminate and second conductor pads on a second surface side of the laminate, and a solder resist layer interposed between the support plate and the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on the opposite side with respect to the first surface of the laminate, the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces exposed from the second surface of the laminate respectively.

公开(公告)号：US20170273180A1

公开(公告)日：2017-09-21

申请号：US15157314

申请日：2016-05-17

Applicant: APPLE INC.

Inventor： David J. Drennan ,  Bruce Berg ,  Joseph Nazari ,  Bonnie W. Tom ,  Kristina A. Babiarz ,  Anthony P. Grazian

IPC: H05K1/05 ,  H04R1/02 ,  H05K3/00 ,  H04R31/00 ,  H05K1/02 ,  H05K3/10

CPC classification number: H04R1/02 ,  B29C45/14311 ,  B29C45/14467 ,  B29C45/14639 ,  B29K2069/00 ,  B29K2715/006 ,  G06F1/1605 ,  G06F1/1626 ,  G06F1/1658 ,  G06F1/1688 ,  H04R31/006 ,  H04R2499/11 ,  H05K1/05 ,  H05K3/202 ,  H05K3/205 ,  H05K3/28 ,  H05K2201/10083 ,  H05K2203/1327

Abstract: A method of forming an overmolded plastic structure on a metallic plate includes first bonding a component to the metallic plate. The component is bonded with an adhesive that adheres it to the metallic plate. A plastic structure is formed over at least a portion of the component and the metallic plate and the plastic structure primarily adheres to the component. The component can be a set of metallic signal conductors that are used to route electrical signals across the metallic plate and the adhesive can be used to electrically insulate the signal conductors from the metallic plate.

公开(公告)号：US20170251552A1

公开(公告)日：2017-08-31

申请号：US15594673

申请日：2017-05-15

Applicant: Subtron Technology Co., Ltd.

Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

IPC: H05K1/09 ,  H05K3/46 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L21/683

CPC classification number: H05K1/09 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/007 ,  H05K3/18 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4638 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2203/03

Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.

公开(公告)号：US20170245365A1

公开(公告)日：2017-08-24

申请号：US15441540

申请日：2017-02-24

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki ISHIHARA ,  Hiroyuki BAN ,  Haiying MEI

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/28 ,  H05K3/02 ,  H05K3/20 ,  H05K3/30 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K1/115 ,  H01L23/49534 ,  H01L2224/16225 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/113 ,  H05K3/0061 ,  H05K3/025 ,  H05K3/205 ,  H05K3/243 ,  H05K3/284 ,  H05K3/303 ,  H05K3/388 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09527 ,  H05K2201/10674 ,  H01L2924/00012

Abstract: A printed wiring board includes a laminate, a wiring layer formed on first main surface of the laminate and including conductor pads, via conductors including first and second via conductors and formed in the laminate such that each via conductor has diameter gradually reducing from the first main surface toward second main surface of the laminate, and conductor post formed on the first via conductors such that each conductor post includes a metal foil and a plating layer formed on the metal foil. The via conductors are formed such that the first via conductors are positioned in an outer edge portion of the laminate and have minimum-diameter-side surfaces positioned to form a same plane with the second main surface of the laminate and that the second via conductors are positioned in a central portion of the laminate and have minimum-diameter-side surfaces recessed from the second main surface of the laminate.

公开(公告)号：US20170096743A1

公开(公告)日：2017-04-06

申请号：US14873602

申请日：2015-10-02

Applicant: Global Solar Energy, Inc.

Inventor： Scott WIEDEMAN

IPC: C25D1/20 ,  C25D1/08 ,  H01L31/02

CPC classification number: C25D1/20 ,  C25D1/04 ,  C25D1/08 ,  H01L31/02008 ,  H01L31/022425 ,  H01L31/18 ,  H05K1/0393 ,  H05K3/205 ,  H05K2201/0108 ,  H05K2203/0726 ,  H05K2203/1545 ,  Y02E10/50

Abstract: A conductive grid formation system, apparatus, and related methods may include a drum having a conductive surface, an insulation layer coating said surface, and a grid pattern formed in the insulation layer to expose portions of the conductive surface. The drum surface may be rotated into and out of a chemical bath, such that a metallic grid is electrodeposited in the exposed portions of the conductive surface. A polymer sheet may be laminated to the surface of the drum and then removed, such that the metallic grid attaches to the polymer sheet and is removed with the polymer sheet. Heat, pressure, and/or adhesive may be utilized in various steps of the process, to facilitate preferential adhesion of the metallic grid to the polymer sheet.