公开(公告)号：US20230084169A1

公开(公告)日：2023-03-16

申请号：US18051151

申请日：2022-10-31

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

公开(公告)号：US20220115316A1

公开(公告)日：2022-04-14

申请号：US17067178

申请日：2020-10-09

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

公开(公告)号：US20190339985A1

公开(公告)日：2019-11-07

申请号：US15967822

申请日：2018-05-01

Applicant: Allegro MicroSystems, LLC

Inventor： Aaron Cook ,  Kenneth Snowdon ,  John Waranowski ,  Virag V. Chaware

IPC: G06F9/4401 ,  G06F1/32 ,  G01R33/06 ,  G01R33/00

Abstract: A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.

公开(公告)号：US10230356B2

公开(公告)日：2019-03-12

申请号：US15890563

申请日：2018-02-07

Applicant: Allegro MicroSystems, LLC

Inventor： Kenneth Snowdon

IPC: H03K3/012 ,  H03K17/687 ,  H03K17/16 ,  H03K17/082 ,  H02M1/08 ,  H02M3/155

Abstract: A high voltage driver includes a high-side output transistor circuit, a differential to single-ended (D2SE) converter connected to a gate of the high-side output transistor circuit, wherein the D2SE is supplied by a first and a second supply voltage, and a high voltage translator connected to the D2SE converter. The D2SE converter and the translator circuit are used to clamp a voltage at the gate of the high-side transistor circuit to be the first supply voltage less the second supply voltage.

公开(公告)号：US12068237B2

公开(公告)日：2024-08-20

申请号：US18051151

申请日：2022-10-31

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/52 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/823493

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

公开(公告)号：US11515246B2

公开(公告)日：2022-11-29

申请号：US17067178

申请日：2020-10-09

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

公开(公告)号：US20180248539A1

公开(公告)日：2018-08-30

申请号：US15890563

申请日：2018-02-07

Applicant: Allegro MicroSystems, LLC

Inventor： Kenneth Snowdon

IPC: H03K3/012 ,  H03K17/687 ,  H03K17/082 ,  H03K17/16

CPC classification number: H03K3/012 ,  H02M1/08 ,  H02M3/155 ,  H03K17/0822 ,  H03K17/165 ,  H03K17/687 ,  H03K2217/0063

Abstract: A high voltage driver includes a high-side output transistor circuit, a differential to single-ended (D2SE) converter connected to a gate of the high-side output transistor circuit, wherein the D2SE is supplied by a first and a second supply voltage, and a high voltage translator connected to the D2SE converter. The D2SE converter and the translator circuit are used to clamp a voltage at the gate of the high-side transistor circuit to be the first supply voltage less the second supply voltage.