公开(公告)号：US20070024178A1

公开(公告)日：2007-02-01

申请号：US11519984

申请日：2006-09-12

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J63/04

CPC classification number: H01J3/021 ,  H01J1/3044 ,  H01J9/185 ,  H01J29/481 ,  H01J31/127

Abstract: An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure includes a conductive structure formed on a substrate. A resistive layer is formed on the conductive structure, and an insulator layer is formed partly over the resistive layer. The contact between the base of the emitter tips and the addressing column line is achieved through a lateral side that is not covered by the insulator layer. The insulator layer helps reduce the possibility of electrical shorting between the addressing column line and the row line structure of the cathode assembly. The insulator layer on top of the addressing column line will allow the use of a thinner subsequent dielectric layer. This thinner dielectric layer, which supports the grid, will provide a lower RC time constant and help achieve better video rate operation. The thinner dielectric layer also will result in smaller grid openings above the tips. This will provide for better beam spots, and, therefore, better image resolution. The thinner dielectric layer will require less applied voltage to extract electrons from the tips, resulting in lower power consumption for the FED.

Abstract translation: 提供FED和制造方法。 FED包括具有改进的柱线结构的阴极组件。 列线结构包括形成在基板上的导电结构。 在导电结构上形成电阻层，部分地在电阻层上形成绝缘体层。 通过未被绝缘体层覆盖的侧面来实现发射极尖端的基极与寻址列线之间的接触。 绝缘体层有助于减少寻址列线和阴极组件的行线结构之间的电短路的可能性。 在寻址列线顶部的绝缘体层将允许使用更薄的后续介电层。 支持电网的这种较薄的介质层将提供较低的RC时间常数，有助于实现更好的视频速率操作。 更薄的介电层也将导致尖端上方的较小的栅极开口。 这将提供更好的光束点，因此，更好的图像分辨率。 更薄的电介质层将需要更少的施加电压以从尖端提取电子，导致FED的较低功耗。

公开(公告)号：US20060172087A1

公开(公告)日：2006-08-03

申请号：US11394988

申请日：2006-03-30

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

IPC: C23C16/14

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

Abstract translation: 公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。 TiCl 4 S和至少一种硅烷首先以等于或高于TiCl 4的第一体积比与硅烷一起进料到室中，持续第一段时间。 该比例足够高以避免钛硅化物在衬底上的可测量沉积。 或者，在第一时间段内没有可测量的硅烷进料到室中。 无论如何，在第一阶段之后，将TiCl 4 S和至少一种硅烷以等于或低于TiCl 4的第二体积比与硅烷一起进料到室中，持续第二阶段 时间。 如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。 无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

公开(公告)号：US07067416B2

公开(公告)日：2006-06-27

申请号：US09941533

申请日：2001-08-29

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L21/28

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine. Boron-doped contacts further possess an increased level of adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms in a high-aspect-ratio opening.

Abstract translation: 提供半导体结构中的导电接触，以及形成导电部件的方法。 该方法包括在衬底上沉积导电材料以填充接触开口，从衬底去除多余的材料，留下开口内的接触，然后在高温下，优选用快速热退火工艺，在 反应气体，以从接触中除去不需要的组分，例如，将氨基钛基氮化钛在氨中热退火以除去接触中的氯，其可以腐蚀上层的铝互连 高浓度 触点对于提供与诸如存储器件的集成电路中的有源部件的电连接是有用的。 在本发明的一个实施方案中，触点包括具有低浓度氯的硼掺杂和/或未掺杂的TiCl 4 S 4氮化钛。 硼掺杂的触点进一步具有增加的对绝缘层的粘附水平，以消除在高纵横比开口中形成厚度大于约200埃的绝缘层时，从接触开口的侧壁剥离和破裂 。

公开(公告)号：US06875626B2

公开(公告)日：2005-04-05

申请号：US10615548

申请日：2003-07-08

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/02 ,  H01L21/00

CPC classification number: H01J9/025

Abstract: A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantial removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.

Abstract translation: 公开了一种用于制造场发射结构的方法。 第一介电层和第二材料层设置在衬底上并且其上具有至少一个发射极尖端。 第二层的平面化暴露了覆盖发射极尖端的第一层的区域，然后可以通过第二层去除哪些区域。 明显去除第二层减少了从第一层的表面突出的任何导电缺陷。 然后形成第三个介电层和第四个栅格层。 第四层的平面化形成网格开口并暴露位于发射极尖端的第三层的介电材料。 然后可以去除一个或两个下层的介电材料以暴露发射极尖端的外表面。

公开(公告)号：US06746952B2

公开(公告)日：2004-06-08

申请号：US09942108

申请日：2001-08-29

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L214763

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L23/485 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.

公开(公告)号：US06713313B2

公开(公告)日：2004-03-30

申请号：US10144490

申请日：2002-05-13

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.

Abstract translation: 用于制造场发射阵列的方法使用单个掩模来限定发射极尖端，它们相应的电阻器，以及可选地导电线路。 将限定发射极尖端和电阻器的一个或多个材料层形成在基本上平行的导线上方和侧向相邻。 发射极尖端和电阻器材料或材料的层的暴露表面可以被平坦化。 然后定义发射极尖端和底层电阻。 导线的基本上纵向的中心部分可以在相邻的发射极尖端之间露出，每个导线的至少一个侧边缘部分被形成发射极尖端和电阻器之后的材料屏蔽。 可以去除导线的暴露部分以便限定导电迹线。 还公开了通过这种方法制造的场发射阵列和显示装置。

公开(公告)号：US06632693B2

公开(公告)日：2003-10-14

申请号：US10157415

申请日：2002-05-29

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.

Abstract translation: 用于在场致发射阵列上制造行线的方法仅使用两个掩模步骤来限定行线和像素开口。 导电材料层设置在半导体材料栅格的基本上平坦化的表面上，并且钝化材料层设置在导电材料层上。 可以通过使用第一掩模通过钝化层和导电层形成行线和像素开口。 可以通过使用第二掩模来进一步限定行线以去除网格的半导体材料。 或者，可以使用第一掩模来完全限定来自钝化层，导电层和半导体材料层的行线，而第二掩模可用于限定通过钝化层和导电材料层的像素开口。 还公开了通过这些方法制造的场致发射阵列

公开(公告)号：US06612891B2

公开(公告)日：2003-09-02

申请号：US10114632

申请日：2002-04-02

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J900

CPC classification number: H01J9/025

Abstract: An emission structure includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. The conductive element may contact the resistor. A method for fabricating the emission structure includes forming at least one conductive line, depositing at least one layer of semiconductive or conductive material over and laterally adjacent the at least one conductive line, and forming a hard mask in recessed areas of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tip and resistor. At least the substantially central longitudinal portion of the conductive trace is removed to form the conductive element.

公开(公告)号：US06383828B2

公开(公告)日：2002-05-07

申请号：US09812367

申请日：2001-03-20

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the present invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array. A second mask is employed to facilitate the removal of passivation material and conductive material from the desired areas of pixel openings. The present invention also includes field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines.

Abstract translation: 一种在场发射阵列上制造行线的方法。 该方法仅采用两个掩模步骤来通过每条行线的选定区域来定义行线和像素开口。 根据本发明的方法，将导电材料层设置在半导体材料格栅的基本上平坦化的表面上。 然后将一层钝化材料设置在导电材料层上。 在该方法的一个实施例中，可以使用第一掩模来从相邻的像素行之间以及从场发射阵列的每个像素的大致上方去除钝化材料和导电材料。 采用第二掩模从相邻的像素行之间移除半导体材料。 在该方法的另一个实施例中，使用第一掩模以便于从场致发射阵列的相邻行像素之间移除钝化材料，导电材料和半导体材料。 使用第二掩模来促进从像素开口的期望区域去除钝化材料和导电材料。 本发明还包括具有半导电栅格的场发射阵列和暴露在相邻行线之间的相对薄的钝化层。

公开(公告)号：US06329744B1

公开(公告)日：2001-12-11

申请号：US09472528

申请日：1999-12-27

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J102

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines. The mask material may be removed and the layer of semiconductive material or conductive material planarized. A mask is disposed over the field emission array and portions of the layer of semiconductive material or conductive material removed therethrough to define emitter tips and their corresponding resistors. The substantially longitudinal center portion of each of the conductive lines may be removed to electrically isolate adjacent columns of pixels of the field emission array from each other. Field emission arrays fabricated by the method of the present invention are also within the scope of the present invention.