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    VARIABLE DELAY CIRCUITRY
    3.
    发明申请
    VARIABLE DELAY CIRCUITRY 有权
    可变延迟电路

    公开(公告)号：US20060208785A1

    公开(公告)日：2006-09-21

    申请号：US11083482

    申请日：2005-03-18

    Applicant: Andy Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    Inventor： Andy Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    IPC: H03H11/26

    CPC classification number: H03K5/133 ,  H03K2005/00058

    Abstract: Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.

    Abstract translation: 用于向集成电路上的其它电路提供输入数据信号的电路包括一个课程延迟链和一个精细延迟链。 如果需要，这两个延迟链是可级联的，以提供可以通过使用精细延迟链精细分级的可能的延迟量的非常宽的范围。

    Differential interconnection circuits in programmable logic devices
    4.
    发明授权
    Differential interconnection circuits in programmable logic devices 有权
    可编程逻辑器件中的差分互连电路

    公开(公告)号：US06515508B1

    公开(公告)日：2003-02-04

    申请号：US09853439

    申请日：2001-05-10

    Applicant: Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    Inventor： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    IPC: H03K19177

    CPC classification number: H03K19/17736 ,  H03K5/151 ,  H03K19/01721 ,  H03K19/17784

    Abstract: At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

    Abstract translation: 可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。 这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。 每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

    External discharging/charging apparatus
    5.
    发明授权
    External discharging/charging apparatus 有权
    外部放电/充电装置

    公开(公告)号：US06291973B1

    公开(公告)日：2001-09-18

    申请号：US09495672

    申请日：2000-02-01

    Applicant: Andy Lee

    Inventor： Andy Lee

    IPC: H02J700

    CPC classification number: H02J7/0031 ,  H02J7/0075 ,  H02J2007/0037

    Abstract: An external discharging/charging apparatus is disclosed. Users can select the operation for directly charging the battery set, or first discharging and then charging the battery set via the external discharging/charging device. Users can directly carry out power discharging/charging to the battery set, thereby improving the accuracy of the detecting device disposed in the battery set and extending the life of the battery set.

    Abstract translation: 公开了一种外部放电/充电装置。 用户可以选择直接对电池组充电的操作，或者先通过外部放电/充电装置对电池组进行放电，然后再充电。 用户可以直接对电池组进行放电/充电，从而提高设置在电池组中的检测装置的精度，延长电池组的使用寿命。

    Programmable logic device incorporating a tristateable logic array block
    6.
    发明授权
    Programmable logic device incorporating a tristateable logic array block 失效
    可编程逻辑器件包含三态逻辑阵列块

    公开(公告)号：US6028809A

    公开(公告)日：2000-02-22

    申请号：US100477

    申请日：1998-06-19

    Applicant: James Schleicher ,  Andy Lee

    Inventor： James Schleicher ,  Andy Lee

    IPC: H03K19/177 ,  G11C8/00

    CPC classification number: H03K19/17748 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    Abstract: The invention relates to an integrated circuit. The integrated circuit can be a programmable logic device that incorporates a multi-function block having a plurality of integrally connected function units where at least one of the function units within the multi-function block is a tristate logic unit. The programmable logic device also includes a tristate bus operatively connected to the tristate logic unit that can supply tristate logic signals to the tristate bus as well as receive tristate logic signals from the tristate bus. The tristate bus carries tristate data signals and address select signals that operate to select a desired one of the tristate logic units within the programmable logic device.

    Abstract translation: 本发明涉及一种集成电路。 集成电路可以是可编程逻辑器件，其包括具有多个整体连接的功能单元的多功能块，其中多功能块中的至少一个功能单元是三态逻辑单元。 可编程逻辑器件还包括可操作地连接到三态逻辑单元的三态总线，其可以向三态总线提供三态逻辑信号以及从三态总线接收三态逻辑信号。 三态总线承载三态数据信号和地址选择信号，其操作以选择可编程逻辑器件内的三态逻辑单元中期望的一个。

    Location identification using broadcast wireless signal signatures
    7.
    发明授权
    Location identification using broadcast wireless signal signatures 有权
    使用广播无线信号签名的位置识别

    公开(公告)号：US08102317B2

    公开(公告)日：2012-01-24

    申请号：US11284800

    申请日：2005-11-22

    Applicant: Andy Lee ,  James J. Spilker, Jr. ,  Matthew Rabinowitz ,  Jimmy K. Omura

    Inventor： Andy Lee ,  James J. Spilker, Jr. ,  Matthew Rabinowitz ,  Jimmy K. Omura

    IPC: G01S3/02

    CPC classification number: G01S5/0252 ,  H04H60/51 ,  H04W64/00

    Abstract: An apparatus comprises a receiver to receive a plurality of wireless television signals each representing a television channel, and a measurement circuit to identify the television channels based on the wireless television signals. One or more of a plurality of possible locations of the apparatus are selected based on identities of the television channels identified by the measurement circuit and a plurality of associations each associating one of the possible locations with identities of the television channels expected at one of the possible locations.

    Abstract translation: 一种装置包括接收多个代表电视频道的无线电视信号的接收机，以及基于无线电视信号识别电视频道的测量电路。 基于由测量电路识别的电视频道的身份，选择多个可能的位置中的一个或多个，每个关联可以将可能位置中的一个与预期的电视频道中的一个相关联， 位置。

    ATSC transmitter identifier signaling
    8.
    发明授权
    ATSC transmitter identifier signaling 有权
    ATSC发射机标识符信令

    公开(公告)号：US07792156B1

    公开(公告)日：2010-09-07

    申请号：US12351841

    申请日：2009-01-11

    Applicant: Andy Lee ,  James J. Spilker, Jr. ,  Matthew Rabinowitz

    Inventor： Andy Lee ,  James J. Spilker, Jr. ,  Matthew Rabinowitz

    IPC: H04J3/06

    CPC classification number: H04J13/105 ,  H04H60/50 ,  H04H60/52 ,  H04J13/0029 ,  H04J13/0048

    Abstract: Apparatus having corresponding computer programs comprise: a code generator adapted to generate a transmitter identification block, wherein the transmitter identification block comprises 32 rows and 82 columns, wherein the first 66 symbols in each of the rows comprises a cyclically-extended 63-chip pseudonoise code that is selectively polarity-inverted according to a respective phase of a 32-chip Walsh code, and wherein each of the last 16 columns comprises a parity-extended 31-chip Gold code that is selectively polarity-inverted according to a respective phase of a 16-chip Walsh code; and a code inserter adapted to insert each of the rows into the reserved block of a respective one of 32 consecutive field synchronization segments in an Advanced Television Systems Committee (ATSC) television signal prior to transmission of the ATSC television signal.

    Abstract translation: 具有对应的计算机程序的装置包括：适于产生发射机识别块的码发生器，其中发射机标识块包括32行和82列，其中每行中的前66个符号包括循环扩展的63码片伪噪声码 其根据32芯片沃尔什码的相应的相位被选择性地极性反转，并且其中最后16列中的每一列包括奇偶校验扩展的31芯片Gold码，其根据相应的相位被选择性地极性反转 16芯片沃尔什码; 以及代码插入器，其适于在传输ATSC电视信号之前将每个行插入高级电视系统委员会（ATSC）电视信号中的32个连续的场同步段中的相应一个的保留块。

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